公开(公告)号：US20220102488A1

公开(公告)日：2022-03-31

申请号：US17493213

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Chia-Hong JAN

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/808 ,  H01L29/8605 ,  H01L27/098

Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

公开(公告)号：US20200066897A1

公开(公告)日：2020-02-27

申请号：US16318108

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Roman W. OLAC-VAW ,  Joodong PARK ,  Chen-Guan LEE ,  Chia-Hong JAN ,  Everett S. CASSIDY-COMFORT

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.

公开(公告)号：US20200066712A1

公开(公告)日：2020-02-27

申请号：US16318107

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Roman W. OLAC-VAW ,  Joodong PARK ,  Chen-Guan LEE ,  Chia-Hong JAN

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H01L21/8234

Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.

公开(公告)号：US20180158906A1

公开(公告)日：2018-06-07

申请号：US15885468

申请日：2018-01-31

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Chia-Hong JAN

IPC: H01L29/06 ,  H01L27/098

CPC classification number: H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

公开(公告)号：US20180114695A1

公开(公告)日：2018-04-26

申请号：US15573458

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Chen-Guan LEE ,  Lu YANG ,  Joodong PARK ,  Chia-Hong JAN

IPC: H01L21/225 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/2255 ,  H01L27/0886 ,  H01L29/0638 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/785

Abstract: Dual height glass is described for doping a fin of a field effect transistor structure in an integrated circuit. In one example, a method includes applying a glass layer over a fin of a FinFET structure, the fin having a source/drain region and a gate region, applying a polysilicon layer over the gate region, removing a portion of the glass layer from the source/drain region after applying the polysilicon, and thermally annealing the glass to drive dopants into the fin, and applying an epitaxial layer over the source/drain region.

公开(公告)号：US20180040637A1

公开(公告)日：2018-02-08

申请号：US15784318

申请日：2017-10-16

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20240038592A1

公开(公告)日：2024-02-01

申请号：US18378983

申请日：2023-10-11

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L21/82345 ,  H01L27/1211 ,  H01L21/845 ,  H01L29/7855 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/4966 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/66545

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20200273887A1

公开(公告)日：2020-08-27

申请号：US15931881

申请日：2020-05-14

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20190305112A1

公开(公告)日：2019-10-03

申请号：US15943556

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/762 ,  H01L27/088

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US20190305111A1

公开(公告)日：2019-10-03

申请号：US15943552

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Christopher KENYON ,  Sridhar GOVINDARAJU ,  Chia-Hong JAN ,  Mark LIU ,  Szuya S. LIAO ,  Walid M. HAFEZ

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.