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    High performance interconnect physical layer
    25.
    发明授权
    High performance interconnect physical layer 有权

    公开(公告)号：US10216674B2

    公开(公告)日：2019-02-26

    申请号：US15393366

    申请日：2016-12-29

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Sitaraman V. Iyer

    IPC: G06F13/40 ,  G06N99/00 ,  G06F13/42

    Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.

    High performance interconnect physical layer
    29.
    发明授权
    High performance interconnect physical layer 有权
    高性能互连物理层

    公开(公告)号：US09208121B2

    公开(公告)日：2015-12-08

    申请号：US14538937

    申请日：2014-11-12

    Applicant: INTEL CORPORATION

    Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Fulvio Spagna ,  Debendra Das Sharma ,  Jeffrey C. Swanson

    IPC: G06F13/42 ,  G06N99/00

    CPC classification number: G06F13/4291 ,  G06F1/24 ,  G06F1/3287 ,  G06F13/1678 ,  G06F13/42 ,  G06F13/4282 ,  G06N99/005

    Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

    Abstract translation: 周期性控制窗口嵌入在要通过串行数据链路发送的链路层数据流中，其中控制窗口被配置为提供物理层信息，包括用于启动数据链路上的状态转换的信息。 可以在数据链路的链路发送状态期间发送链路层数据，并且控制窗口可以中断发送猝发。 在一个方面，信息包括指示改变链路上的活动车道数目的尝试的链路宽度转换数据。

    Fast deskew when exiting low-power partial-width high speed link state
    30.
    发明授权
    Fast deskew when exiting low-power partial-width high speed link state 有权
    当退出低功率部分宽度高速链路状态时，快速的偏移校正

    公开(公告)号：US09183171B2

    公开(公告)日：2015-11-10

    申请号：US13631876

    申请日：2012-09-29

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Debendra Das Sharma ,  Robert G. Blankenship ,  Darren S. Jue

    IPC: G06F1/32 ,  G06F13/42 ,  G06F13/38

    CPC classification number: G06F13/42 ,  G06F1/3253 ,  G06F13/38 ,  G06F13/382 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Methods and apparatus relating to fast deskew when exiting a low-power partial-width high speed link state are described. In one embodiment, an exit flit on active lanes and/or a wake signal/sequence on idle lanes may be transmitted at a first point in time to cause one or more idle lanes of a link to enter an active state. At a second point in time (following or otherwise subsequent to the first point in time), training sequences are transmitted over the one or more idle lanes of the link. And, the one or more idle lanes are deskewed in response to the training sequences and prior to a third point in time (following or otherwise subsequent to the second point in time). Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了在退出低功率部分宽度高速链路状态时与快速偏移校正有关的方法和装置。 在一个实施例中，可以在第一时间点上传输有效车道上的出口飞行和/或空闲车道上的唤醒信号/序列，以使链路的一个或多个空闲车道进入活动状态。 在第二时间点（在第一时间点之后或之后），在链路的一个或多个空闲车道上发送训练序列。 并且，一个或多个空闲车道响应于训练序列而在第三时间点之前（在第二时间点之后或之后的其他时间）进行了偏斜校正。 还公开并要求保护其他实施例。

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