公开(公告)号：US20230006065A1

公开(公告)日：2023-01-05

申请号：US17899429

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Willy RACHMADY ,  Jack T. KAVALIEROS ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Sean T. MA ,  Harold KENNEL ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US20220352032A1

公开(公告)日：2022-11-03

申请号：US17866122

申请日：2022-07-15

Applicant: INTEL CORPORATION

Inventor： Aaron D. LILAK ,  Ehren MANNEBACH ,  Anh PHAN ,  Richard E. SCHENKER ,  Stephanie A. BOJARSKI ,  Willy RACHMADY ,  Patrick R. MORROW ,  Jeffrey D. BIELEFELD ,  Gilbert DEWEY ,  Hui Jae YOO

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L23/532 ,  H01L23/48

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

公开(公告)号：US20220102522A1

公开(公告)日：2022-03-31

申请号：US17033499

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Nazila HARATIPOUR ,  Siddharth CHOUKSEY ,  Arnab SEN GUPTA ,  Christopher J. JEZEWSKI ,  I-Cheng TUNG ,  Matthew V. METZ ,  Anand S. MURTHY

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: Low resistance and reduced reactivity approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is on the first or second semiconductor source or drain structure, the source or drain contact including an alloyed metal barrier layer and an inner conductive structure.

公开(公告)号：US20220102510A1

公开(公告)日：2022-03-31

申请号：US17033362

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Kevin COOK ,  Anand S. MURTHY ,  Gilbert DEWEY ,  Nazila HARATIPOUR ,  Ralph Thomas TROEGER ,  Christopher J. JEZEWSKI ,  I-Cheng TUNG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/45 ,  H01L27/092 ,  H01L21/8238

Abstract: Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.

公开(公告)号：US20210242325A1

公开(公告)日：2021-08-05

申请号：US17236338

申请日：2021-04-21

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Mark L. DOCZY ,  Suman DATTA ,  Justin K. BRASK ,  Matthew V. METZ

IPC: H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

公开(公告)号：US20200335635A1

公开(公告)日：2020-10-22

申请号：US16957617

申请日：2018-03-22

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY

IPC: H01L29/786 ,  H01L29/423

Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.

公开(公告)号：US20200295153A1

公开(公告)日：2020-09-17

申请号：US16889680

申请日：2020-06-01

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Mark L. DOCZY ,  Suman DATTA ,  Justin K. BRASK ,  Matthew V. METZ

IPC: H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

公开(公告)号：US20200211905A1

公开(公告)日：2020-07-02

申请号：US16236156

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Gilbert DEWEY ,  Aaron LILAK ,  Kimin JUN ,  Brennen MUELLER ,  Ehren MANNEBACH ,  Anh PHAN ,  Patrick MORROW ,  Hui Jae YOO ,  Jack T. KAVALIEROS

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200066326A1

公开(公告)日：2020-02-27

申请号：US15776058

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Rafael RIOS ,  Gilbert DEWEY ,  Van H. LE ,  Jack KAVALIEROS ,  Mesut METERELLIYOZ

IPC: G11C11/4097 ,  G11C11/405 ,  H01L27/108

Abstract: A high retention time memory element is described that has dual gate devices. In one example, the memory element has a write transistor with a metal gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.

公开(公告)号：US20190305136A1

公开(公告)日：2019-10-03

申请号：US15943584

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sean MA ,  Abhishek SHARMA ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Van H. LE

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/49 ,  H01L27/12

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.