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公开(公告)号：US20140310543A1
公开(公告)日：2014-10-16
申请号：US14148530
申请日：2014-01-06
Applicant: Intel Corporation
Inventor： Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsake , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC: G06F1/32
CPC classification number: G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
Abstract: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
Abstract translation: 一种降低平台空闲链路功率的方法和装置。 在本发明的一个实施例中，主机及其在平台中的耦合端点各自具有低功率空闲链路状态，其允许在主机及其耦合的端点中禁用高速链路电路。 这允许平台减少其空闲功率，因为在本发明的一个实施例中，主机及其耦合端点能够关闭其高速链路电路。
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公开(公告)号：US10528345B2
公开(公告)日：2020-01-07
申请号：US14671914
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Ilan Pardo , Oren Ben-Kiki , Arch D. Robison , Nadav Chachmon , James H. Cownie
Abstract: Instructions and logic provide atomic range operations in a multiprocessing system. In one embodiment an atomic range modification instruction specifies an address for a set of range indices. The instruction locks access to the set of range indices and loads the range indices to check the range size. The range size is compared with a size sufficient to perform the range modification. If the range size is sufficient to perform the range modification, the range modification is performed and one or more modified range indices of the set of range indices is stored back to memory. Otherwise an error signal is set when the range size is not sufficient to perform said range modification. Access to the set of range indices is unlocked responsive to completion of the atomic range modification instruction. Embodiments may include atomic increment next instructions, add next instructions, decrement end instructions, and/or subtract end instructions.
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公开(公告)号：US10083037B2
公开(公告)日：2018-09-25
申请号：US15281944
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC: G06F9/38 , G06F9/30 , G06F11/07 , G06F9/54 , G06F12/0875
CPC classification number: G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
Abstract: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among the SMT cores, and at least one L2 cache circuit to store both instructions and data. The processor further comprises a communication interconnect circuit including a PCIe circuit to communicatively couple one or more of the SMT cores to an accelerator device, the PCIe circuit to provide the accelerator device access to resources of the processor including the at least one shared cache circuit. The processor further comprises a memory access circuit to identify an accelerator context save/restore region in a memory determined by an accelerator context save/restore value, the accelerator context save/restore region to store an accelerator context state.
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公开(公告)号：US20170123475A1
公开(公告)日：2017-05-04
申请号：US15180466
申请日：2016-06-13
Applicant: Intel Corporation
Inventor： Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC: G06F1/32
CPC classification number: G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
Abstract: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
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25.发明申请公开(公告)号：US20160283245A1
公开(公告)日：2016-09-29
申请号：US14671475
申请日：2015-03-27
Applicant: INTEL CORPORATION
Inventor： Oren Ben-Kiki , Ilan Pardo , Arch D. Robison , James H. Cownie
CPC classification number: G06F9/3822 , G06F9/30087 , G06F9/3009 , G06F9/3806 , G06F9/3851 , G06F9/3877 , G06F9/46 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/0895 , G06F2212/1016 , G06F2212/283 , G06F2212/452 , G06F2212/6028
Abstract: A processor of an aspect includes a plurality of processor elements, and a first processor element. The first processor element may perform a user-level fork instruction of a software thread. The first processor element may include a decoder to decode the user-level fork instruction. The user-level fork instruction is to indicate at least one instruction address. The first processor element may also include a user-level thread fork module. The user-level fork module, in response to the user-level fork instruction being decoded, may configure each of the plurality of processor elements to perform instructions in parallel. Other processors, methods, systems, and instructions are disclosed.
Abstract translation: 一方面的处理器包括多个处理器元件和第一处理器元件。 第一处理器元件可以执行软件线程的用户级叉指令。 第一处理器元件可以包括用于解码用户级叉指令的解码器。 用户级fork指令至少指示一个指令地址。 第一处理器元件还可以包括用户级线程分支模块。 用户级叉模块响应于被解码的用户级fork指令，可以配置多个处理器元件中的每一个并行执行指令。 公开了其他处理器，方法，系统和指令。
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Patent Agency Ranking
公开(公告)号：US09098415B2
公开(公告)日：2015-08-04
申请号：US13691016
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
CPC classification number: G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。
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公开(公告)号：US20150149683A9
公开(公告)日：2015-05-28
申请号：US13691016
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC: G06F13/40
CPC classification number: G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。
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公开(公告)号：US10346195B2
公开(公告)日：2019-07-09
申请号：US13730971
申请日：2012-12-29
Applicant: Intel Corporation
Inventor： Oren Ben-Kiki , Ilan Pardo , Eliezer Weissmann , Robert Valentine , Yuval Yosef
Abstract: A processor is described having logic circuitry of a general purpose CPU core to save multiple copies of context of a thread of the general purpose CPU core to prepare multiple micro-threads of a multi-threaded accelerator for execution to accelerate operations for the thread through parallel execution of the micro-threads.
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公开(公告)号：US10255077B2
公开(公告)日：2019-04-09
申请号：US15226875
申请日：2016-08-02
Applicant: Intel Corporation
Inventor： Oren Ben-Kiki , Yuval Yosef , Ilan Pardo , Dror Markovich
Abstract: An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.
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公开(公告)号：US10185385B2
公开(公告)日：2019-01-22
申请号：US15180466
申请日：2016-06-13
Applicant: Intel Corporation
Inventor： Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC: G06F1/32
Abstract: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
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