公开(公告)号：US20160294394A1

公开(公告)日：2016-10-06

申请号：US15182486

申请日：2016-06-14

Applicant: INTEL CORPORATION

Inventor： Amit R. Trivedi ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Muhammad M. Khellah ,  James W. Tschanz

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/356113

Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.

Abstract translation: 实施例包括用于在低电压域和高电压域之间电压移位数据信号的装置，方法和系统。 在实施例中，电压电平移位器电路可以包括自适应保持器电路，增强的可中断电源电路和/或电容升压电路，以减小由电压电平移位器电路支持的低电压域的最小电压。 可以描述和要求保护其他实施例。

公开(公告)号：US20230273832A1

公开(公告)日：2023-08-31

申请号：US18133616

申请日：2023-04-12

Applicant: Intel Corporation

Inventor： Somnath Paul ,  Muhammad M. Khellah ,  Linda Zeng ,  Mohamed Elmalaki

IPC: G06F9/50 ,  G06F1/3228 ,  G06F1/3296

CPC classification number: G06F9/505 ,  G06F1/3228 ,  G06F1/3296

Abstract: A system for autonomous and proactive power management for energy efficient execution of machine learning workloads may include an apparatus such as system-on-chip (SoC) comprising an accelerator configurable to load and execute a neural network and circuitry to receive a profile of the neural network. The profile may be received from a compiler and include information regarding a plurality of layers of the neural network. Responsive to the profile and the information regarding the plurality of layers, circuitry may adjust, using a local power management unit (PMU) included the apparatus, a power level to the accelerator while the accelerator executes the neural network. The power level adjustment may be based on whether the particular layer is a compute-intensive layer or a memory-intensive layer.

公开(公告)号：US11176994B2

公开(公告)日：2021-11-16

申请号：US17001432

申请日：2020-08-24

Applicant: Intel Corporation

Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418 ,  G11C7/22

Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

公开(公告)号：US10748060B2

公开(公告)日：2020-08-18

申请号：US15294666

申请日：2016-10-14

Applicant: Intel Corporation

Inventor： Somnath Paul ,  Charles Augustine ,  Muhammad M. Khellah

IPC: G06N3/08 ,  G06N20/00 ,  G06N3/04 ,  G06N3/063

Abstract: A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response to detecting the incoming data signal. The circuitry is further to, responsive to detecting an end of the time window: retrieve, from the memory, a weight value for a post-synaptic neuromorphic state for which an outgoing data signal is generated during the time window, the post-synaptic neuromorphic state being a fan-out connection of the pre-synaptic neuromorphic state; perform a causal update to the weight value, according to a learning function, to generate an updated weight value; and store the updated weight value back to the memory.

公开(公告)号：US10528473B2

公开(公告)日：2020-01-07

申请号：US15621401

申请日：2017-06-13

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Muhammad M. Khellah ,  Vivek De ,  Ming Zhang ,  Jaume Abella ,  Javier Carretero Casado ,  Pedro Chaparro Monferrer ,  Xavier Vera ,  Antonio Gonzalez

IPC: G06F12/00 ,  G06F12/0864 ,  G06F12/0804 ,  G06F1/3234

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

公开(公告)号：US10359834B2

公开(公告)日：2019-07-23

申请号：US15409366

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Muhammad M. Khellah ,  James W. Tschanz

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.

公开(公告)号：US20190206456A1

公开(公告)日：2019-07-04

申请号：US16234065

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Muhammad M. Khellah

IPC: G11C7/12 ,  G11C15/04 ,  G11C11/412 ,  G11C8/16 ,  G11C7/18 ,  G11C11/419 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/18 ,  G11C8/16 ,  G11C11/412 ,  G11C11/419 ,  G11C15/04

Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.

公开(公告)号：US20180322384A1

公开(公告)日：2018-11-08

申请号：US15584510

申请日：2017-05-02

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Somnath Paul ,  Sadique Ul Ameen Sheik ,  Muhammad M. Khellah

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04

Abstract: A spike sent from a first artificial neuron in a spiking neural network (SNN) to a second artificial neuron in the SNN is identified, with the spike sent over a particular artificial synapse in the SNN. The membrane potential of the second artificial neuron at a particular time step, corresponding to sending of the spike, is compared to a threshold potential, where the threshold potential is set lower than a firing potential of the second artificial neuron. A change to the synaptic weight of the particular artificial synapse is determined based on the spike, where the synaptic weight is to be decreased if the membrane potential of the second artificial neuron is lower than the threshold potential at the particular time step and the synaptic weight is to be increased if the membrane potential of the second artificial neuron is higher than the threshold potential at the particular time step.

公开(公告)号：US20180191347A1

公开(公告)日：2018-07-05

申请号：US15394296

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Andrea Bonetti ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Minki Cho ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: H03K19/0185 ,  H03K19/21

CPC classification number: H03K19/018521 ,  H03K19/21

Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.

公开(公告)号：US09766827B1

公开(公告)日：2017-09-19

申请号：US15151402

申请日：2016-05-10

Applicant: Intel Corporation

Inventor： Pascal A. Meinerzhagen ,  Stephen T. Kim ,  Anupama A. Thaploo ,  Muhammad M. Khellah

IPC: G05F1/613 ,  G06F3/06 ,  G11C5/14

CPC classification number: G11C5/148

Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.