公开(公告)号：US20230074199A1

公开(公告)日：2023-03-09

申请号：US17986715

申请日：2022-11-14

Applicant: Intel Corporation

Inventor： Glenn GLASS ,  Anand MURTHY ,  Biswajeet GUHA ,  Dax M. CRUM ,  Sean MA ,  Tahir GHANI ,  Susmita GHOSE ,  Stephen CEA ,  Rishabh MEHANDRU

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

公开(公告)号：US20220165855A1

公开(公告)日：2022-05-26

申请号：US17667493

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Pratik A. PATEL ,  Thomas T. TROEGER ,  Szuya S. LIAO

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

公开(公告)号：US20220157984A1

公开(公告)日：2022-05-19

申请号：US17589831

申请日：2022-01-31

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Tahir GHANI ,  Stephen CEA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

公开(公告)号：US20220123128A1

公开(公告)日：2022-04-21

申请号：US17567753

申请日：2022-01-03

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side . A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

公开(公告)号：US20200066851A1

公开(公告)日：2020-02-27

申请号：US16465489

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Pratik A. PATEL ,  Thomas T. TROEGER ,  Szuya S. LIAO

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/45 ,  H01L29/49 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L21/321 ,  H01L29/40 ,  H01L29/66

Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

公开(公告)号：US20190355756A1

公开(公告)日：2019-11-21

申请号：US15774556

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  Rishabh MEHANDRU

IPC: H01L27/12 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/06

Abstract: A dynamic logic circuit including a first transistor within a first device stratum of a substrate; and a second transistor within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode. A method including disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and forming a common gate electrode on each of the semiconductor body and the second semiconductor body.

公开(公告)号：US20190311950A1

公开(公告)日：2019-10-10

申请号：US15945914

申请日：2018-04-05

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  H01L29/66

Abstract: Wrap-around contact structures for semiconductor fins, and methods of fabricating wrap-around contact structures for semiconductor fins, are described. In an example, an integrated circuit structure includes a semiconductor fin having a first portion protruding through a trench isolation region. A gate structure is over a top and along sidewalls of the first portion of the semiconductor fin. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor fin. The epitaxial structure has substantially vertical sidewalls in alignment with the second portion of the semiconductor fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor fin and along the substantially vertical sidewalls of the epitaxial structure.

公开(公告)号：US20190221577A1

公开(公告)日：2019-07-18

申请号：US16324479

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Patrick THEOFANIS ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Stephen M. CEA

IPC: H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11575

Abstract: An apparatus including an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, wherein each of the at least two vertically stacked layers includes a laterally disposed contact point; and an electrically conductive interconnection coupled to a lateral edge of the contact point of each of the at least two vertically stacked layers and bridging the dielectric layer. A method including forming an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, forming a trench that exposes a lateral contact point of each of the at least two vertically stacked layers; depositing a polymer in the trench, wherein the polymer preferentially aligns to a material of the lateral contact point and bridges the dielectric layer; and modifying or replacing the polyconductive material.

公开(公告)号：US20190027503A1

公开(公告)日：2019-01-24

申请号：US15752241

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Patrick MORROW ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Cory E. WEBER

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/265 ,  H01L21/3115

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

公开(公告)号：US20180212057A1

公开(公告)日：2018-07-26

申请号：US15747111

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Patrick MORROW ,  Patrick H. KEYS

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

Abstract: Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region.