公开(公告)号：US20180006951A1

公开(公告)日：2018-01-04

申请号：US15201394

申请日：2016-07-02

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Daniel Rivas Barragan

IPC: H04L12/803 ,  H04L29/08 ,  H04L12/26

CPC classification number: H04L43/08 ,  G06F9/505 ,  H04L43/0817 ,  H04L43/0852 ,  H04L43/0888 ,  H04L43/0894 ,  H04L47/822 ,  H04L49/505 ,  H04L67/1002 ,  H04L67/1023

Abstract: Examples may include techniques to distribute queries in a fabric of nodes configured to process the queries. A load balancing switch coupled to the nodes can receive indications of resource metrics from the nodes and can schedule and distribute the queries based on the resource metrics and network metrics identified by the switch. The switch can include programmable circuitry to receive selected resource metrics and identify selected network metrics and to distribute queries to nodes based on the metrics and distribution logic.

公开(公告)号：US20170116133A1

公开(公告)日：2017-04-27

申请号：US14921809

申请日：2015-10-23

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Martin P. Dimitrov ,  Thomas Willhalm

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/00 ,  G06F12/0862 ,  G06F13/16 ,  G06F2212/1024 ,  G06F2212/221

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

公开(公告)号：US20160283354A1

公开(公告)日：2016-09-29

申请号：US14670965

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Philip R. Lantz ,  Thomas Willhalm ,  Kirill Instrumentov ,  Karthik Kumar

IPC: G06F11/36

CPC classification number: G06F11/3688 ,  G06F11/3648

Abstract: Technologies for software testing include a computing device having persistent memory that includes a platform simulator and an application or other code module to be tested. The computing device generates a checkpoint for the application at a test location using the platform simulator. The computing device executes the application from the test location to an end location and traces all writes to persistent memory using the platform simulator. The computing device generates permutations of persistent memory writes that are allowed by the hardware specification of the computing device simulated by the platform simulator. The computing device replays each permutation from the checkpoint, simulates a power failure, and then invokes a user-defined test function using the platform simulator. The computing device may test different permutations of memory writes until the application's use of persistent memory is validated. Other embodiments are described and claimed.

Abstract translation: 用于软件测试的技术包括具有持久存储器的计算设备，其包括平台模拟器和要测试的应用或其他代码模块。 计算设备使用平台模拟器在测试位置生成应用程序的检查点。 计算设备从测试位置执行应用程序到终端位置，并使用平台模拟器跟踪对持久存储器的所有写入。 计算设备产生由平台模拟器模拟的计算设备的硬件规范允许的持久存储器写入的排列。 计算设备从检查点重播每个置换，模拟电源故障，然后使用平台模拟器调用用户定义的测试功能。 计算设备可以测试存储器写入的不同排列，直到应用程序使用永久存储器被验证为止。 描述和要求保护其他实施例。

公开(公告)号：US20160246723A1

公开(公告)日：2016-08-25

申请号：US14628954

申请日：2015-02-23

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Thomas Willhalm

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30192 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/621

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a vector cache line write back instruction. The vector cache line write back instruction is to indicate a source packed memory indices operand that is to include a plurality of memory indices. The processor also includes a cache coherency system coupled with the packed data registers and the decode unit. The cache coherency system, in response to the vector cache line write back instruction, to cause, any dirty cache lines, in any caches in a coherency domain, which are to have stored therein data for any of a plurality of memory addresses that are to be indicated by any of the memory indices of the source packed memory indices operand, to be written back toward one or more memories. Other processors, methods, and systems are also disclosed.

Abstract translation: 一方面的处理器包括多个压缩数据寄存器，以及解码单元，用于解码向量高速缓存线回写指令。 向量高速缓存线回写指令是指示要包括多个存储器索引的源打包存储器索引操作数。 处理器还包括与压缩数据寄存器和解码单元耦合的高速缓存一致性系统。 高速缓存一致性系统响应于向量高速缓存行回写指令，导致在一致性域中的任何高速缓存中的任何脏高速缓存行，其将存储多个存储器地址中的任何一个的数据 由源打包存储器索引操作数的任何存储器索引指示，以被写回到一个或多个存储器。 还公开了其他处理器，方法和系统。

公开(公告)号：US20150261534A1

公开(公告)日：2015-09-17

申请号：US14142738

申请日：2014-03-13

Applicant: Intel Corporation

Inventor： Tal Uliel ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mark J. Charney ,  Thomas Willhalm

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

Abstract: A processor includes a decoder to receive an instruction that indicates first and second source packed data operands and at least one shift count. An execution unit is operable, in response to the instruction, to store a result packed data operand. Each result data element includes a first least significant bit (LSB) portion of a first data element of a corresponding pair of data elements in a most significant bit (MSB) portion, and a second MSB portion of a second data element of the corresponding pair in a LSB portion. One of the first LSB portion of the first data element and the second MSB portion of the second data element has a corresponding shift count number of bits. The other has a number of bits equal to a size of a data element of the first source packed data minus the corresponding shift count.

Abstract translation: 处理器包括解码器，用于接收指示第一和第二源压缩数据操作数和至少一个移位计数的指令。 执行单元响应于该指令可操作地存储结果打包数据操作数。 每个结果数据元素包括最高有效位（MSB）部分中对应的一对数据元素的第一数据元素的第一最低有效位（LSB）部分和相应对的第二数据元素的第二MSB部分 在LSB部分。 第一数据元素的第一LSB部分和第二数据元素的第二MSB部分之一具有相应的移位计数位数。 另一个具有等于第一源打包数据的数据元素减去相应移位计数的大小的位数。

公开(公告)号：US12088507B2

公开(公告)日：2024-09-10

申请号：US17861949

申请日：2022-07-11

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Mark A. Schmisseur ,  Timothy Verrall

IPC: G06F15/173 ,  G06F9/50 ,  G06N20/00 ,  H04L47/70 ,  H04L47/765 ,  H04L47/83

CPC classification number: H04L47/765 ,  G06F9/5011 ,  G06N20/00 ,  H04L47/824 ,  H04L47/83

Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.

公开(公告)号：US12058036B2

公开(公告)日：2024-08-06

申请号：US17746677

申请日：2022-05-17

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj Ramanujan ,  Brian Slechta

IPC: H04L45/302 ,  H04L47/125 ,  H04L47/26 ,  H04L49/10 ,  H04L49/20

CPC classification number: H04L45/302 ,  H04L47/125 ,  H04L47/26 ,  H04L49/10 ,  H04L49/205

Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.

公开(公告)号：US12019768B2

公开(公告)日：2024-06-25

申请号：US16830703

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mark Schmisseur ,  Thomas Willhalm

IPC: G06F21/60 ,  G06F3/06 ,  H04W12/50

CPC classification number: G06F21/606 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  H04W12/50

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to process memory operation requests from a memory controller, and provide a front end interface to remote pooled memory hosted at a near edge device. An embodiment of another electronic apparatus may include local memory and logic communicatively coupled the local memory, the logic to allocate a range of the local memory as remote pooled memory, and provide a back end interface to the remote pooled memory for memory requests from a far edge device. Other embodiments are disclosed and claimed.

公开(公告)号：US11567683B2

公开(公告)日：2023-01-31

申请号：US16368152

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Timothy Verrall ,  Ned Smith

IPC: G06F3/06 ,  G06F12/02 ,  G06F16/901 ,  G06F12/1072 ,  G06F17/17

Abstract: Technologies for providing deduplication of data in an edge network includes a compute device having circuitry to obtain a request to write a data set. The circuitry is also to apply, to the data set, an approximation function to produce an approximated data set. Additionally, the circuitry is to determine whether the approximated data set is already present in a shared memory and write, to a translation table and in response to a determination that the approximated data set is already present in the shared memory, an association between a local memory address and a location, in the shared memory, where the approximated data set is already present. Additionally, the circuitry is to increase a reference count associated with the location in the shared memory.

公开(公告)号：US20220407803A1

公开(公告)日：2022-12-22

申请号：US17746677

申请日：2022-05-17

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj Ramanujan ,  Brian Slechta

IPC: H04L45/302 ,  H04L47/125 ,  H04L49/10 ,  H04L47/26 ,  H04L49/20

Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.