公开(公告)号：US10978573B2

公开(公告)日：2021-04-13

申请号：US16504739

申请日：2019-07-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Yogendra ,  Ardasheir Rahman ,  Robert Robison ,  Adra Carr

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L29/78 ,  H01L29/08

Abstract: Semiconductor devices and methods of forming the same include forming a dummy gate on a stack of alternating channel layers and sacrificial layers. A spacer layer is formed over the dummy gate and the stack. Portions of the spacer layer on horizontal surfaces of the stack are etched away to form vertical spacers. Exposed portions of the stack are etched away. Semiconductor material is grown from exposed sidewalls of remaining channel layers to form source and drain structures that are constrained in lateral dimensions by the vertical spacers.

公开(公告)号：US10896965B2

公开(公告)日：2021-01-19

申请号：US16692809

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Adra Carr ,  Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Pouya Hashemi

IPC: H01L29/786 ,  H01L29/417 ,  H01L21/768 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

公开(公告)号：US10886376B2

公开(公告)日：2021-01-05

申请号：US16692741

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Adra Carr ,  Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Pouya Hashemi

IPC: H01L29/417 ,  H01L29/786 ,  H01L21/768 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

公开(公告)号：US20200335392A1

公开(公告)日：2020-10-22

申请号：US16387687

申请日：2019-04-18

Applicant: International Business Machines Corporation

Inventor： Adra Carr ,  Vimal Kamineni ,  Ruilong Xie ,  Andrew Greene ,  Nigel Cave ,  Veeraraghavan Basker

IPC: H01L21/768

Abstract: Embodiments of the present invention are directed to reducing the effective capacitance between active devices at the contact level. In a non-limiting embodiment of the invention, an interlayer dielectric is replaced with a low-k material without damaging a self-aligned contact (SAC) cap. A gate can be formed over a channel region of a fin. The gate can include a gate spacer and a SAC cap. Source and drain regions can be formed adjacent to the channel region. A contact is formed on the SAC cap and on surfaces of the source and drain regions. A first dielectric layer can be recessed to expose a sidewall of the contact and a sidewall of the gate spacer. A second dielectric layer can be formed on the recessed surface of the first dielectric layer. The second dielectric layer can include a dielectric material having a dielectric constant less than the first dielectric layer.

公开(公告)号：US20200013900A1

公开(公告)日：2020-01-09

申请号：US16026521

申请日：2018-07-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Adra Carr ,  Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Pouya Hashemi

IPC: H01L29/786 ,  H01L21/768 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/45

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

公开(公告)号：US20200006648A1

公开(公告)日：2020-01-02

申请号：US16566349

申请日：2019-09-10

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Oscar van der Straten ,  Adra Carr ,  Praneet Adusumilli

IPC: H01L45/00

Abstract: A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.

公开(公告)号：US20200006647A1

公开(公告)日：2020-01-02

申请号：US16566311

申请日：2019-09-10

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Oscar van der Straten ,  Adra Carr ,  Praneet Adusumilli

IPC: H01L45/00

Abstract: A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.

公开(公告)号：US10395925B2

公开(公告)日：2019-08-27

申请号：US15857124

申请日：2017-12-28

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Adra Carr ,  Shanti Pancharatnam ,  Indira Seshadri ,  Yasir Sulehria

IPC: H01L21/00 ,  H01L21/033 ,  H01L21/027 ,  G03F7/11 ,  H01L21/308 ,  G03F7/30 ,  G03F7/20

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is formed such that an interface portion of the hard mask layer proximate the resist layer has a higher metal content than other portions of the hard mask layer. The method further includes exposing the patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, etching the hard mask layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The hard mask layer illustratively includes metal oxide, metal nitride and/or metal oxynitride, and may exhibit an elevated surface hydrophobicity due to its high metal content interface portion.