公开(公告)号：US12040373B2

公开(公告)日：2024-07-16

申请号：US17551428

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Nicolas Loubet ,  Christian Lavoie ,  Adra Carr ,  Nicholas Anthony Lanzillo

IPC: H01L29/45 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/456 ,  H01L29/401 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate including designated source or drain (source/drain) regions. An active source/drain is in the designated source/drain regions, and a source/drain cap liner is on an upper surface of the active source/drain. The semiconductor device further includes trench silicide regions completely filed with a silicide material.

公开(公告)号：US20230187521A1

公开(公告)日：2023-06-15

申请号：US17551428

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Nicolas Loubet ,  Christian Lavoie ,  Adra Carr ,  Nicholas Anthony Lanzillo

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/456 ,  H01L29/401 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate including designated source or drain (source/drain) regions. An active source/drain is in the designated source/drain regions, and a source/drain cap liner is on an upper surface of the active source/drain. The semiconductor device further includes trench silicide regions completely filed with a silicide material.

公开(公告)号：US10586872B2

公开(公告)日：2020-03-10

申请号：US16026521

申请日：2018-07-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Adra Carr ,  Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Pouya Hashemi

IPC: H01L29/786 ,  H01L21/768 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/45

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

公开(公告)号：US20190341546A1

公开(公告)日：2019-11-07

申请号：US15968213

申请日：2018-05-01

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Oscar van der Straten ,  Adra Carr ,  Praneet Adusumilli

IPC: H01L45/00

Abstract: A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.

公开(公告)号：US20210090950A1

公开(公告)日：2021-03-25

申请号：US16578300

申请日：2019-09-21

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Adra Carr ,  Ruilong Xie ,  Kangguo Cheng

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: MOL non-SAC structures and techniques for formation thereof are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming gates over the fins and source/drains offset by gate spacers; lining upper sidewalls of the gates with a first dielectric liner; depositing a source/drain metal; lining upper sidewalls of the source/drain metal with a second dielectric liner; depositing a dielectric over the gates and source/drains; forming a first via in the dielectric which exposes the second dielectric liner over a select source/drain; removing the second dielectric liner from the select source/drain; forming a second via in the dielectric which exposes the first dielectric liner over a select gate; removing the first dielectric liner from the select gate; forming a source/drain contact in the first via; and forming a gate contact in the second via. A semiconductor device is also provided.

公开(公告)号：US20210013321A1

公开(公告)日：2021-01-14

申请号：US16504739

申请日：2019-07-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Yogendra ,  Ardasheir Rahman ,  Robert Robison ,  Adra Carr

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L27/092

Abstract: Semiconductor devices and methods of forming the same include forming a dummy gate on a stack of alternating channel layers and sacrificial layers. A spacer layer is formed over the dummy gate and the stack. Portions of the spacer layer on horizontal surfaces of the stack are etched away to form vertical spacers. Exposed portions of the stack are etched away. Semiconductor material is grown from exposed sidewalls of remaining channel layers to form source and drain structures that are constrained in lateral dimensions by the vertical spacers.

公开(公告)号：US10770562B1

公开(公告)日：2020-09-08

申请号：US16290182

申请日：2019-03-01

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Andrew Greene ,  Vimal Kamineni ,  Adra Carr ,  Chanro Park ,  Ruilong Xie

IPC: H01L21/00 ,  H01L29/45 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3105 ,  H01L21/321 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/762

Abstract: Techniques are provided for fabricating a semiconductor integrated circuit device which implement an interlayer dielectric (ILD) layer replacement process to replace an initial sacrificial ILD layer with a low-k ILD layer, while forming silicide or dielectric capping layers to protect source/drain contacts of field-effect transistor devices from etch damage during the ILD replacement process. For example, source/drain contact openings (e.g., trenches) are formed in a sacrificial ILD layer and metallic source/drain contacts are formed in the source/drain contact openings. Protective capping layers (e.g., metal-semiconductor alloy capping layers or dielectric capping layers) are formed on upper surfaces of the metallic source/drain contacts. The sacrificial ILD layer is removed using an etch process to etch down the sacrificial ILD layer selective to the protective capping layers, and a low-k ILD layer is formed in place of the removed sacrificial ILD layer.

公开(公告)号：US10446746B1

公开(公告)日：2019-10-15

申请号：US15968213

申请日：2018-05-01

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Oscar van der Straten ,  Adra Carr ,  Praneet Adusumilli

IPC: H01L21/64 ,  H01L45/00

Abstract: A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.

公开(公告)号：US20200279918A1

公开(公告)日：2020-09-03

申请号：US16290611

申请日：2019-03-01

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Ruqiang Bao ,  Junli Wang ,  Lan Yu ,  Reinaldo Vega ,  Adra Carr

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

公开(公告)号：US20200098927A1

公开(公告)日：2020-03-26

申请号：US16692741

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Adra Carr ,  Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Pouya Hashemi

IPC: H01L29/786 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.