公开(公告)号：US12178137B2

公开(公告)日：2024-12-24

申请号：US17444176

申请日：2021-07-30

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dimitri Houssameddine ,  Saba Zare ,  Karthik Yogendra

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A memory device with in-array magnetic shield includes an electrically conductive structure embedded within an interconnect dielectric material located above a first metal layer. The electrically conductive structure includes a bottom electrode. The memory device further includes a magnetic tunnel junction stack located above the bottom electrode, a dielectric filling layer surrounding the magnetic tunnel junction stack, one or more connecting vias extending through the dielectric filling layer and the interconnect dielectric material until a top portion of the first metal layer, and one or more dummy vias located between the one or more connecting vias and the magnetic tunnel junction stack for conducting an external magnetic field around the memory device.

公开(公告)号：US20230031478A1

公开(公告)日：2023-02-02

申请号：US17444176

申请日：2021-07-30

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dimitri Houssameddine ,  Saba Zare ,  Karthik Yogendra

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A memory device with in-array magnetic shield includes an electrically conductive structure embedded within an interconnect dielectric material located above a first metal layer. The electrically conductive structure includes a bottom electrode. The memory device further includes a magnetic tunnel junction stack located above the bottom electrode, a dielectric filling layer surrounding the magnetic tunnel junction stack, one or more connecting vias extending through the dielectric filling layer and the interconnect dielectric material until a top portion of the first metal layer, and one or more dummy vias located between the one or more connecting vias and the magnetic tunnel junction stack for conducting an external magnetic field around the memory device.

公开(公告)号：US20220173308A1

公开(公告)日：2022-06-02

申请号：US17105699

申请日：2020-11-27

Applicant: International Business Machines Corporation

Inventor： Karthik Yogendra ,  Praneet Adusumilli

IPC: H01L45/00 ,  H01L27/24

Abstract: A method for forming an in-situ drift-mitigation liner on a sidewall of a phase-change material (PCM) device stack includes providing an intermediate device including a substrate including a bottom wiring portion, a bottom electrode metal layer, a drift-mitigation liner layer, an active area layer, a carbon layer, a top electrode metal layer, patterning the top electrode metal layer to form a top electrode, performing a first intermediate angle ion beam etch (IBE), etching the carbon layer and the active area layer, which are formed on the drift-mitigation liner, to form a carbon portion and an active area portion of the PCM device stack, and performing a low angle IBE, etching the drift-mitigation liner and redepositing material etched from the drift-mitigation liner as a conductive liner material on sidewalls of the PCM device stack including exposed portions of the carbon portion, the active area portion, and the top electrode.

公开(公告)号：US20210013321A1

公开(公告)日：2021-01-14

申请号：US16504739

申请日：2019-07-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Yogendra ,  Ardasheir Rahman ,  Robert Robison ,  Adra Carr

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L27/092

Abstract: Semiconductor devices and methods of forming the same include forming a dummy gate on a stack of alternating channel layers and sacrificial layers. A spacer layer is formed over the dummy gate and the stack. Portions of the spacer layer on horizontal surfaces of the stack are etched away to form vertical spacers. Exposed portions of the stack are etched away. Semiconductor material is grown from exposed sidewalls of remaining channel layers to form source and drain structures that are constrained in lateral dimensions by the vertical spacers.

公开(公告)号：US20230240148A1

公开(公告)日：2023-07-27

申请号：US17648816

申请日：2022-01-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Yogendra ,  Heng Wu ,  Saba Zare ,  Dimitri Houssameddine

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02 ,  G11C11/161 ,  G11C11/1675

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, a first metal line above the MTJ stack and a magnetoelectric material layer above the first metal line. A semiconductor device including an array of magnetic tunnel junction (MTJ) stacks, a first metal line connected physically and electrically to a top electrode of each MTJ stack in a row of the array of MTJ stacks and a magnetoelectric material layer above the first metal line, connected physically and electrically to the first metal line. A method including forming an array of magnetic tunnel junction (MTJ) stacks, forming a first metal line above a row of the array of MTJ stacks, and forming a magnetoelectric material layer above the first metal line, connected physically and electrically to the first metal line.

公开(公告)号：US20230131445A1

公开(公告)日：2023-04-27

申请号：US17510436

申请日：2021-10-26

Applicant: International Business Machines Corporation

Inventor： Saba Zare ,  Dimitri Houssameddine ,  Karthik Yogendra ,  Heng Wu

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A device includes a Magnetic Tunnel Junction (MTJ) memory element comprising, a reference layer, a free layer, and a magnetic tunneling layer between the reference layer and the free layer; and a pair of magneto-electric controlling layers, which have in-plane uniaxial anisotropy, wherein the pair of magneto-electric controlling layers are disposed below the free layer.

公开(公告)号：US20220392504A1

公开(公告)日：2022-12-08

申请号：US17336994

申请日：2021-06-02

Applicant: International Business Machines Corporation

Inventor： Dimitri Houssameddine ,  Saba Zare ,  Heng Wu ,  Karthik Yogendra

IPC: G11C11/16 ,  H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  G11C27/00

Abstract: A memory system may include a magnetic tunnel junction stack, a first high resistance tunnel barrier, and a first voltage controlled magnetic anisotropy write layer. The first voltage controlled magnetic anisotropy write layer may be adjacent the high resistance tunnel barrier, and the voltage controlled magnetic anisotropy write line may include a magnetic material in direct contact with a high resistance tunnel barrier.

公开(公告)号：US11456413B2

公开(公告)日：2022-09-27

申请号：US17105699

申请日：2020-11-27

Applicant: International Business Machines Corporation

Inventor： Karthik Yogendra ,  Praneet Adusumilli

IPC: H01L27/24 ,  H01L45/00

Abstract: A method for forming an in-situ drift-mitigation liner on a sidewall of a phase-change material (PCM) device stack includes providing an intermediate device including a substrate including a bottom wiring portion, a bottom electrode metal layer, a drift-mitigation liner layer, an active area layer, a carbon layer, a top electrode metal layer, patterning the top electrode metal layer to form a top electrode, performing a first intermediate angle ion beam etch (IBE), etching the carbon layer and the active area layer, which are formed on the drift-mitigation liner, to form a carbon portion and an active area portion of the PCM device stack, and performing a low angle IBE, etching the drift-mitigation liner and redepositing material etched from the drift-mitigation liner as a conductive liner material on sidewalls of the PCM device stack including exposed portions of the carbon portion, the active area portion, and the top electrode.

公开(公告)号：US10593870B2

公开(公告)日：2020-03-17

申请号：US15841872

申请日：2017-12-14

Applicant: International Business Machines Corporation

Inventor： Hiroyuki Miyazoe ,  Nathan P. Marchack ,  HsinYu Tsai ,  Eugene J. O'Sullivan ,  Karthik Yogendra

IPC: H01L21/3213 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  H01L21/28 ,  H01L21/033

Abstract: A method of forming a semiconductor structure includes forming a first spacer material over two or more mandrels disposed over a magnetoresistive random-access memory (MRAM) stack. The method also includes performing a first sidewall image transfer of the two or more mandrels to form a first set of fins of the first spacer material over the MRAM stack, and performing a second sidewall image transfer to form a plurality of pillars of the first spacer material over the MRAM stack. The pillars of the first spacer material form top electrodes for a plurality of MRAM cells patterned from the MRAM stack.

公开(公告)号：US12112782B2

公开(公告)日：2024-10-08

申请号：US17469350

申请日：2021-09-08

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Karthik Yogendra ,  Dimitri Houssameddine ,  Kangguo Cheng ,  Ruilong Xie

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: An approach for minimizing stack height and reducing resistance of an MRAM (Magnetoresistive random-access memory) is disclosed. The approach leverages an MRAM device with a T shape magnetic bottom electrode. The T shape magnetic bottom electrode can be made from a lower resistance metal such as cobalt. Furthermore, the method of creating the MRAM can include, depositing a low-k dielectric layer, forming bottom electrode via within the low-k dielectric layer, depositing bottom electrode metal liner on the bottom electrode via, depositing bottom electrode magnetic metal on the bottom electrode metal liner, planarizing the bottom electrode magnetic metal, depositing coupling layer and an MRAM stack on the bottom electrode magnetic metal, patterning and etching anisotropically the MRAM stack and depositing in-situ conformal dielectric layer and forming a top contact via on the MRAM stack.