公开(公告)号：US20190312141A1

公开(公告)日：2019-10-10

申请号：US16450367

申请日：2019-06-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.

公开(公告)号：US20190312044A1

公开(公告)日：2019-10-10

申请号：US16437383

申请日：2019-06-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Michael A. Guillorn ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/112 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L23/525

Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.

公开(公告)号：US10438956B2

公开(公告)日：2019-10-08

申请号：US15615248

申请日：2017-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Michael A. Guillorn ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L23/525 ,  H01L29/772 ,  H01L27/112 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L27/06 ,  H01L21/84

Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.

公开(公告)号：US10396202B2

公开(公告)日：2019-08-27

申请号：US15888794

申请日：2018-02-05

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786 ,  H01L29/08

Abstract: A semiconductor structure includes a plurality of stacked and suspended semiconductor nanosheets located above a semiconductor substrate. Each semiconductor nanosheet has a pair of end sidewalls that have a V-shaped undercut surface. A functional gate structure is located around the plurality of stacked and suspended semiconductor nanosheets, and a source/drain (S/D) semiconductor material structure is located on each side of the functional gate structure. In accordance with the present application, sidewall portions of each S/D semiconductor material structure are in direct contact with the V-shaped undercut surface of the end sidewalls of each of the semiconductor nanosheets.

公开(公告)号：US10381349B2

公开(公告)日：2019-08-13

申请号：US15689473

申请日：2017-08-29

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC: H01L27/098 ,  H01L21/8232 ,  H01L29/66 ,  H01L29/808 ,  H01L29/423

Abstract: A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.

公开(公告)号：US10361301B2

公开(公告)日：2019-07-23

申请号：US15783693

申请日：2017-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234

Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

公开(公告)号：US10312337B2

公开(公告)日：2019-06-04

申请号：US15462372

申请日：2017-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/786 ,  H01L29/40 ,  H01L29/775

Abstract: A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.

公开(公告)号：US10283601B2

公开(公告)日：2019-05-07

申请号：US15467801

申请日：2017-03-23

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/02 ,  H01L21/283 ,  H01L29/165 ,  H01L29/423

Abstract: A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having a gate spacer including a lower portion that fills in a undercut region that lies adjacent to the strained silicon germanium alloy fin and beneath raised source/drain (S/D) structures and silicon pedestal structures that can provide improved overlay capacitance.

公开(公告)号：US10256230B2

公开(公告)日：2019-04-09

申请号：US15426739

申请日：2017-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/861

Abstract: A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

公开(公告)号：US10249630B2

公开(公告)日：2019-04-02

申请号：US15815326

申请日：2017-11-16

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Karthik Balakrishnan ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/11507 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L49/02

Abstract: After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.