公开(公告)号：US20240312912A1

公开(公告)日：2024-09-19

申请号：US18182412

申请日：2023-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： REINALDO VEGA ,  Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Brent A. Anderson

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A microelectronic structure including a plurality of nanosheet transistors. Each of the plurality of nanosheet transistors includes an active gate located around a plurality of active channel layers and each of the plurality of nanosheet transistors includes a source/drain region have a first length. The first length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. A power via located between a first dummy device and a second dummy device and the power via has second length. The second length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. The second length is larger than the first length.

公开(公告)号：US20240290713A1

公开(公告)日：2024-08-29

申请号：US18174692

申请日：2023-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Ruilong Xie ,  REINALDO VEGA ,  Lawrence A. Clevenger ,  Brent A. Anderson

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76892 ,  H01L23/5226

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level, the metal level includes a metal strip including a notch at a side of the metal strip or a pass-through inside the metal strip, wherein the notch or the pass-through is at least partially filled with a dielectric material. The metal level further includes a conductive wiring that vertically passes through the metal strip. The conductive wiring is at least partially inside the notch or inside the pass-through and is insulated from the metal strip by the dielectric material. Methods of manufacturing the semiconductor structure are also provided.

公开(公告)号：US20240203870A1

公开(公告)日：2024-06-20

申请号：US18083818

申请日：2022-12-19

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Albert M. Chu ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  REINALDO VEGA ,  Ruilong Xie

IPC: H01L23/522 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L29/7827

Abstract: A semiconductor structure is provided that includes a MOL and/or BEOL structure for low resistance, low capacitance and design flexibility. The structure includes a first metal level including a plurality of first metal lines and a plurality of first metal vias located at same level within a first interlayer dielectric material layer, and a second metal level located above the first metal level. The second metal level includes a plurality of second metal lines and a plurality of second metal vias located at a same level within a second interlayer dielectric material layer. The first metal level is formed utilizing a damascene process and the second metal level is formed utilizing a substrative etch. A single metallization is used to provide the first and second metal levels.

公开(公告)号：US20240194601A1

公开(公告)日：2024-06-13

申请号：US18062624

申请日：2022-12-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Albert M. Chu ,  Nicholas Anthony Lanzillo ,  Albert M. Young ,  Junli Wang ,  Brent A. Anderson ,  Ruilong Xie ,  Lawrence A. Clevenger ,  REINALDO VEGA

IPC: H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L23/5286 ,  G06F30/392 ,  G06F30/394 ,  H01L23/5226 ,  H01L27/0922

Abstract: A semiconductor structure is presented having a plurality of circuit rows, a plurality of first power rails positioned on front sides of the plurality of circuit rows, a plurality of second power rails positioned on back sides of the plurality of circuit rows, and power tap cells associated with each the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality the second power rails. In one instance, the plurality of second power rails are orthogonal to the plurality of first power rails. in another instance, the plurality of first power rails are horizontally offset from the plurality of second power rails. The one or more power vias include at least two or more different sized power vias.

公开(公告)号：US20240153867A1

公开(公告)日：2024-05-09

申请号：US17983863

申请日：2022-11-09

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Albert M. Chu ,  REINALDO VEGA ,  Ruilong Xie ,  Lawrence A. Clevenger ,  Brent A. Anderson

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/5286

Abstract: A semiconductor structure is provided that includes a device layer and a non-perpendicular (or non-orthogonal) wiring layer that includes a skip-level via that connects this wiring level to the device layer. The skip-level via passes through another wiring layer that is positioned between the non-perpendicular wiring layer and the device layer, without physically contacting any metal lines that are present in this another wiring layer.

公开(公告)号：US20240113178A1

公开(公告)日：2024-04-04

申请号：US17957599

申请日：2022-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. Anderson ,  Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Lawrence A. Clevenger ,  REINALDO VEGA

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41741 ,  H01L21/28518 ,  H01L29/401 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/7827

Abstract: Semiconductor device and methods of forming the same include a semiconductor channel. A top source/drain structure is on the semiconductor channel. A bottom source/drain structure is under the semiconductor channel. The bottom source/drain structure includes a doped semiconductor part and a conductor part, with the conductor part covering a bottom surface of the doped semiconductor part.

公开(公告)号：US20240088018A1

公开(公告)日：2024-03-14

申请号：US17943799

申请日：2022-09-13

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Ruilong Xie ,  REINALDO VEGA ,  Albert M. Chu

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/528

Abstract: A skip-level via structure is provided that electrically connects a third level of interconnect wiring to a first level of interconnect wiring or a fourth level of interconnect wiring to a first level of interconnect wiring. In the first instance, the skip-level via structure enables connection even when the first level of interconnect wiring and the third level of interconnect wiring do not line up. In the second instance, the skip-level via structure enables a low resistance connection of the fourth level of interconnect wiring to the first level of interconnect wiring due to increased contact area.

公开(公告)号：US20230282523A1

公开(公告)日：2023-09-07

申请号：US17688873

申请日：2022-03-07

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  REINALDO VEGA ,  Praneet Adusumilli ,  Cheng Chi

IPC: H01L21/8238 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L29/517 ,  H01L29/518 ,  H01L29/4958 ,  H01L29/4966

Abstract: A transistor structure includes a semiconductor substrate; an NFET channel structure atop the substrate; a PFET channel structure atop the substrate; a first dielectric atop the PFET channel structure; a second dielectric atop the NFET channel structure; a shared internal metal gate atop the dielectrics; a shared ferroelectric layer atop the shared internal metal gate; and a shared external gate electrode atop the shared ferroelectric layer. The first and second dielectrics are doped with different metals that provide differing overall work functions for the PFET and the NFET. A method for making a transistor structure includes depositing a shared dielectric onto an NFET channel structure and a PFET channel structure, and converting the shared dielectric to a first high-k dielectric atop the PFET channel structure and a second high-k dielectric atop the NFET channel structure. The first high-k dielectric and the second high-k dielectric are doped with different metals.

公开(公告)号：US20220416056A1

公开(公告)日：2022-12-29

申请号：US17358275

申请日：2021-06-25

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Ruilong Xie ,  REINALDO VEGA ,  Kangguo Cheng ,  Lan Yu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/786

Abstract: Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

公开(公告)号：US20220392995A1

公开(公告)日：2022-12-08

申请号：US17341489

申请日：2021-06-08

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  REINALDO VEGA ,  David Wolpert ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L49/02 ,  H01L29/51

Abstract: A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.