DIELECTRIC TUNING OF NEGATIVE CAPACITANCE IN DUAL CHANNEL FIELD EFFECT TRANSISTORS

    公开(公告)号:US20230282523A1

    公开(公告)日:2023-09-07

    申请号:US17688873

    申请日:2022-03-07

    Abstract: A transistor structure includes a semiconductor substrate; an NFET channel structure atop the substrate; a PFET channel structure atop the substrate; a first dielectric atop the PFET channel structure; a second dielectric atop the NFET channel structure; a shared internal metal gate atop the dielectrics; a shared ferroelectric layer atop the shared internal metal gate; and a shared external gate electrode atop the shared ferroelectric layer. The first and second dielectrics are doped with different metals that provide differing overall work functions for the PFET and the NFET. A method for making a transistor structure includes depositing a shared dielectric onto an NFET channel structure and a PFET channel structure, and converting the shared dielectric to a first high-k dielectric atop the PFET channel structure and a second high-k dielectric atop the NFET channel structure. The first high-k dielectric and the second high-k dielectric are doped with different metals.

    FULL NANOSHEET AIRGAP SPACER
    29.
    发明申请

    公开(公告)号:US20220416056A1

    公开(公告)日:2022-12-29

    申请号:US17358275

    申请日:2021-06-25

    Abstract: Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

    MULTILAYER DIELECTRIC FOR METAL-INSULATOR-METAL CAPACITOR

    公开(公告)号:US20220392995A1

    公开(公告)日:2022-12-08

    申请号:US17341489

    申请日:2021-06-08

    Abstract: A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.

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