公开(公告)号：US20240113219A1

公开(公告)日：2024-04-04

申请号：US17936434

申请日：2022-09-29

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Albert M. Chu ,  Nicholas Anthony Lanzillo ,  Ruilong Xie ,  Lawrence A. Clevenger ,  REINALDO VEGA

IPC: H01L29/78 ,  H01L23/528 ,  H01L23/535 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/535 ,  H01L29/41741 ,  H01L29/4175

Abstract: A VTFET is provided on a wafer. A backside power delivery network is on a backside of the wafer. A first backside contact is connected to a bottom source/drain region of the VTFET and a first portion of the backside power delivery network. A second backside contact is connected to top source/drain region of the VTFET and a second portion of the backside power delivery network.

公开(公告)号：US20240006346A1

公开(公告)日：2024-01-04

申请号：US17854125

申请日：2022-06-30

Applicant: International Business Machines Corporation

Inventor： Cheng Chi ,  Takashi Ando ,  REINALDO VEGA ,  Praneet Adusumilli

IPC: H01L23/00

CPC classification number: H01L23/573

Abstract: An integrated circuit includes a semiconductor substrate; a logic area, located outward of the semiconductor substrate; and a physically unclonable function (PUF) area, located outward of the semiconductor substrate. The logic area includes a plurality of logic metal-insulator-metal decoupling capacitors with at least three plates. The PUF area includes a plurality of PUF metal-insulator-metal capacitors with at least three plates. Shorts and opens are avoided in the logic area, while the PUF metal-insulator-metal capacitors exhibit deliberately-introduced shorts and opens that function as a PUF.

公开(公告)号：US20240006315A1

公开(公告)日：2024-01-04

申请号：US17854305

申请日：2022-06-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  REINALDO VEGA ,  David Wolpert ,  Kisik Choi

IPC: H01L23/528 ,  H01L23/535 ,  H01L23/498 ,  H01L21/8238 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L23/535 ,  H01L23/49822 ,  H01L21/823871 ,  H01L21/76898

Abstract: A semiconductor array structure includes a substrate; a plurality of field effect transistors (FETs) arranged in rows and located on the substrate, each comprising a first source-drain region, a second source-drain region, at least one channel coupling the source-drain regions, and a gate adjacent the at least one channel. A plurality of frontside signal lines are on a front side of the FETs; a plurality of backside power rails are on a back side of the FETs; a plurality of backside signal wires are on the back side. Frontside signal connections run from the frontside signal lines to the first source-drain regions; Power connections run from the backside power rails to the second source-drain regions; and backside gate contact connections run from the backside signal wires to the gates. The backside gate contact connections each have a bottom dimension larger than the gate length.

公开(公告)号：US20230422461A1

公开(公告)日：2023-12-28

申请号：US17808178

申请日：2022-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： REINALDO VEGA ,  Takashi Ando ,  Praneet Adusumilli ,  David Wolpert ,  Cheng Chi

IPC: H01L27/11 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L27/1104 ,  H01L23/5286 ,  H01L28/40

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate. The decoupling capacitor is also connected to a second gate. As such, the decoupling capacitor separates the first gate from the second gate. The decoupling capacitor may include a dielectric liner within a gate cut trench and a ferroelectric material over the dielectric liner. A second power rail may be connected to the decoupling capacitor by way of the second gate. The first gate and the second gate may be inline with respect thereto.

公开(公告)号：US20230420530A1

公开(公告)日：2023-12-28

申请号：US17849639

申请日：2022-06-25

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  REINALDO VEGA ,  Julien Frougier ,  Kangguo Cheng

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/66439 ,  H01L29/0665

Abstract: A semiconductor structure includes a common substrate; a first forksheet complementary metal oxide semiconductor (CMOS) device that is located on the common substrate and that has an nFET (n-doped Field Effect Transistor) and a pFET (p-doped Field Effect Transistor) and has a first β (effective width ratio) between the nFET and the pFET; and a second forksheet device that is adjacent to the first forksheet device on the common substrate and that has a second β between a second nFET and a second pFET. The second β is different than the first β by at least 5 percent. Another semiconductor structure includes a common substrate; a forksheet complementary metal oxide semiconductor (CMOS) device that is located on the common substrate; and a gate-all-around (GAA) nanosheet CMOS device that is located on the common substrate and is adjacent to the forksheet device.

公开(公告)号：US20230387238A1

公开(公告)日：2023-11-30

申请号：US17664712

申请日：2022-05-24

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Andrew M. Greene ,  REINALDO VEGA

IPC: H01L29/45 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L29/45 ,  H01L27/0924 ,  H01L29/0847 ,  H01L21/823821 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823871

Abstract: A complementary metal oxide semiconductor (CMOS) device. The device includes a pFET epi and an nFET epi. The pFET epi includes a single dielectric layer that wraps around a first portion of the pFET epi and a confined trench epi on a second portion of the pFET epi that is adjacent a first contact. The nFET epi includes a bi-layer dielectric liner that wraps around a first portion of the nFET epi and a second portion of the nFET epi that is adjacent a second contact.

公开(公告)号：US20240234523A9

公开(公告)日：2024-07-11

申请号：US18049297

申请日：2022-10-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Brent A. Anderson ,  REINALDO VEGA ,  Albert M. Chu ,  Lawrence A. Clevenger

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

公开(公告)号：US20240105610A1

公开(公告)日：2024-03-28

申请号：US17936202

申请日：2022-09-28

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Albert M. Chu ,  Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  REINALDO VEGA

IPC: H01L23/528 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L29/41741 ,  H01L29/7827

Abstract: A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first width and the first width is a contacted poly pitch (CPP). The first backside contact may be at least the first width from the VTFET. The first backside contact may be double the first width from the VTFET.

公开(公告)号：US20230168297A1

公开(公告)日：2023-06-01

申请号：US17536211

申请日：2021-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pablo Nieves ,  KUSHAGRA SINHA ,  REINALDO VEGA

IPC: G01R31/28 ,  G01R31/319 ,  H01L21/66

CPC classification number: G01R31/2891 ,  G01R31/31905 ,  G01R31/2884 ,  H01L22/34

Abstract: A system includes probe pins each including a probe tip and a plurality of thermocouples arranged such that at least one thermocouple is positioned between a pair of the probe pins. The plurality of thermocouples can be placed adjacent or above a device under test (DUT). The probe tips of the probe pins are placed over a plurality of pads. The plurality of thermocouples are placed adjacent or between the plurality of pads. The at least one thermocouple positioned between the pair of the probe pins can be either a single thermocouple or a thermocouple array.

公开(公告)号：US20230089185A1

公开(公告)日：2023-03-23

申请号：US17447944

申请日：2021-09-17

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  REINALDO VEGA ,  Alexander Reznicek ,  Kangguo Cheng

IPC: H01L27/092 ,  H01L27/12 ,  H01L23/538 ,  H01L21/8234

Abstract: An integrated circuit component includes a first layer including first and second areas of epitaxy material. The first layer has a first polarity. The component further includes a second layer including third and fourth areas of epitaxy material. The second layer has a second polarity that is different than the first polarity. The third area is arranged at least partially above the first area, and the fourth area is arranged at least partially above the second area. The integrated circuit component further includes an interconnect in direct contact with one of the first area and the third area and in direct contact with one of the second area and the fourth area. The interconnect has a top surface that does not extend substantially above an uppermost surface of the second layer.