公开(公告)号：US20200243670A1

公开(公告)日：2020-07-30

申请号：US16844228

申请日：2020-04-09

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  Choonghyun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762

Abstract: According to an embodiment of the present invention, a semiconductor structure includes a semiconductor substrate and a plurality of fins located on the semiconductor substrate. The plurality of fins each independently includes a bottom fin portion, a top fin portion layer, and an isolated oxide layer located in between the bottom fin portion and the top fin portion layer in the y-direction parallel to the height of the plurality of fins. The isolated oxide layer includes a mixed oxide region located in between oxidized regions in an x-direction perpendicular to the height of the plurality of fins.

公开(公告)号：US20200243526A1

公开(公告)日：2020-07-30

申请号：US16847350

申请日：2020-04-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Junli Wang ,  Michael P. Belyansky

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/285

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

公开(公告)号：US20200243525A1

公开(公告)日：2020-07-30

申请号：US16847122

申请日：2020-04-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Junli Wang ,  Michael P. Belyansky

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/285

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

公开(公告)号：US20200227322A1

公开(公告)日：2020-07-16

申请号：US16835882

申请日：2020-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Shogo Mochizuki ,  Gen Tsutsui ,  Ruqiang Bao

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311

Abstract: Semiconductor devices include a substrate layer and a semiconductor layer formed over the substrate layer. A dielectric layer fills a gap between the semiconductor layer and the substrate layer, on end faces of the semiconductor layer, and on a top surface of the semiconductor layer.

公开(公告)号：US20200185380A1

公开(公告)日：2020-06-11

申请号：US16788216

申请日：2020-02-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Ruqiang Bao ,  Hemanth Jagannathan ,  ChoongHyun Lee

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/098

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

公开(公告)号：US20200091319A1

公开(公告)日：2020-03-19

申请号：US16133763

申请日：2018-09-18

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  Choonghyun Lee

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/78

Abstract: According to an embodiment of the present invention, a semiconductor structure includes a semiconductor substrate and a plurality of fins located on the semiconductor substrate. The plurality of fins each independently includes a bottom fin portion, a top fin portion layer, and an isolated oxide layer located in between the bottom fin portion and the top fin portion layer in the y-direction parallel to the height of the plurality of fins. The isolated oxide layer includes a mixed oxide region located in between oxidized regions in an x-direction perpendicular to the height of the plurality of fins.

公开(公告)号：US20200083349A1

公开(公告)日：2020-03-12

申请号：US16681016

申请日：2019-11-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Kisup Chung ,  Andrew M. Greene ,  Sivananda K. Kanakasabapathy ,  David L. Rath ,  Indira P.V. Seshadri ,  Rajasekhar Venigalla

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/535 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/08

Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner

公开(公告)号：US10586767B2

公开(公告)日：2020-03-10

申请号：US16039570

申请日：2018-07-19

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Cornelius Brown Peethala ,  Michael Rizzolo ,  Koichi Motoyama ,  Gen Tsutsui ,  Ruqiang Bao ,  Gangadhara Raja Muthinti ,  Lawrence A. Clevenger

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/48 ,  H01L21/768 ,  H01L21/306

Abstract: A method for fabricating semiconductor wafers comprises creating a semiconductor wafer having a plurality of wide copper wires and a plurality of narrow copper wires embedded in a dielectric insulator. The width of each wide copper wire is greater than a cutoff value and each narrow copper is less than the cutoff value. An optical pass through layer is deposited over a top surface of the wafer and a photo-resist layer is deposited over the optical pass through layer. The wafer is exposed to a light source to selectively remove photo-resist, forming a self-aligned pattern where photo-resist only remains in areas above wide copper wires. The self-aligned pattern is transferred to the optical pass through layer and the remaining photo-resist is removed. The wafer is chemically etched to remove the narrow copper wires, defining narrow gaps in the dielectric insulator. The wafer is metallized with non-copper metal, forming narrow non-copper metal wires.

公开(公告)号：US20200066603A1

公开(公告)日：2020-02-27

申请号：US16106396

申请日：2018-08-21

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Brent A. Anderson ,  ChoongHyun Lee

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.

公开(公告)号：US10553498B2

公开(公告)日：2020-02-04

申请号：US15828822

申请日：2017-12-01

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092

Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.