公开(公告)号：US09035383B2

公开(公告)日：2015-05-19

申请号：US13967807

申请日：2013-08-15

Applicant: International Business Machines Corporation

Inventor： Sarunya Bangsaruntip ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L49/02 ,  H01L21/84 ,  H01L27/12 ,  H01L21/77 ,  B82Y40/00 ,  H01L27/06

CPC classification number: H01L21/77 ,  B82Y40/00 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66181 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/861 ,  H01L29/94 ,  Y10S977/762

Abstract: A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.

Abstract translation: 一种制造电子装置的方法包括以下步骤。 在SOI晶片的SOI层中蚀刻至少一个第一组和至少一个第二组纳米线和衬垫。 形成第一栅极堆叠，其围绕用作电容器器件的沟道区域的第一组纳米线的每一个的至少一部分。 形成第二栅极堆叠，其围绕用作FET器件的沟道区域的第二组纳米线的每一个的至少一部分。 FET器件的源极和漏极区域被选择性地掺杂。 第一硅化物形成在至少延伸到第一栅极堆叠的边缘的电容器器件的源极和漏极区域上。 第二硅化物形成在FET器件的源极和漏极区域上。

公开(公告)号：US08809957B2

公开(公告)日：2014-08-19

申请号：US14050921

申请日：2013-10-10

Applicant: International Business Machines Corporation

Inventor： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Leland Chang ,  Jeffrey W. Sleight

IPC: H01L27/12

CPC classification number: H01L27/1211 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3247 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/78696

Abstract: Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.

Abstract translation: 提供了混合纳米线FET和FinFET器件及其制造方法。 一方面，制造具有纳米线FET和finFET的CMOS电路的方法包括以下步骤。 提供了在BOX上具有活性层的晶片。 有源层的第一区域变薄。 有机平面化层沉积在有源层上。 使用第一硬掩模在有源层的第一区域中蚀刻纳米线和焊盘。 纳米线悬挂在BOX上。 使用第二硬掩模在活性层的第二区域中蚀刻金箔。 形成围绕每个纳米线的至少一部分的第一栅极堆叠。 形成第二栅极堆叠，覆盖每个散热片的至少一部分。 在纳米线，焊盘和鳍片的暴露部分上生长外延材料。

公开(公告)号：US20140027855A1

公开(公告)日：2014-01-30

申请号：US14050921

申请日：2013-10-10

Applicant: International Business Machines Corporation

Inventor： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Leland Chang ,  Jeffrey W. Sleight

IPC: H01L27/12

CPC classification number: H01L27/1211 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3247 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/78696

Abstract: Hybrid nanowire FET and FinFET devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a CMOS circuit having a nanowire FET and a finFET includes the following steps. A wafer is provided having an active layer over a BOX. A first region of the active layer is thinned. An organic planarizing layer is deposited on the active layer. Nanowires and pads are etched in the first region of the active layer using a first hardmask. The nanowires are suspended over the BOX. Fins are etched in the second region of the active layer using a second hardmask. A first gate stack is formed that surrounds at least a portion of each of the nanowires. A second gate stack is formed covering at least a portion of each of the fins. An epitaxial material is grown on exposed portions of the nanowires, pads and fins.

Abstract translation: 提供了混合纳米线FET和FinFET器件及其制造方法。 一方面，制造具有纳米线FET和finFET的CMOS电路的方法包括以下步骤。 提供了在BOX上具有活性层的晶片。 有源层的第一区域变薄。 有机平面化层沉积在有源层上。 使用第一硬掩模在有源层的第一区域中蚀刻纳米线和焊盘。 纳米线悬挂在BOX上。 使用第二硬掩模在活性层的第二区域中刻蚀金属丝。 形成围绕每个纳米线的至少一部分的第一栅极堆叠。 形成第二栅极堆叠，覆盖每个散热片的至少一部分。 在纳米线，焊盘和鳍片的暴露部分上生长外延材料。

公开(公告)号：US20210280766A1

公开(公告)日：2021-09-09

申请号：US16728504

申请日：2019-12-27

Applicant: International Business Machines Corporation

Inventor： Baleegh Abdo ,  Sarunya Bangsaruntip

IPC: H01L39/24 ,  G06N10/00

Abstract: Techniques for trapping quasiparticles in superconductor devices are provided. A superconductor device can comprise a substrate layer. The superconductor device can further comprise a first superconductor layer composed of a first superconductor material, on a first surface of a substrate layer. The superconductor device can further comprise a trapping material buried in the first superconductor layer, wherein the trapping material is formulated to trap quasiparticles.

公开(公告)号：US10546924B2

公开(公告)日：2020-01-28

申请号：US15426677

申请日：2017-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sarunya Bangsaruntip ,  Michael Engel ,  Shu-Jen Han

IPC: H01L29/06 ,  H01L21/28 ,  H01L51/05 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L51/00 ,  H01L21/285 ,  H01L21/02

Abstract: A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

公开(公告)号：US20180269412A1

公开(公告)日：2018-09-20

申请号：US15461175

申请日：2017-03-16

Applicant: International Business Machines Corporation

Inventor： Ali Afzali-Ardakani ,  Sarunya Bangsaruntip ,  Shu-Jen Han ,  HsinYu Tsai

IPC: H01L51/05 ,  H01L51/00

CPC classification number: H01L51/0558 ,  H01L51/0003 ,  H01L51/0012 ,  H01L51/0049 ,  H01L51/0093 ,  H01L51/0545 ,  H01L2251/303

Abstract: In one aspect, a method for placing carbon nanotubes on a dielectric includes: using DSA of a block copolymer to create a pattern in the placement guide layer on the dielectric which includes multiple trenches in the placement guide layer, wherein there is a first charge on sidewall and top surfaces of the trenches and a second charge on bottom surfaces of the trenches, and wherein the first charge is different from the second charge; and depositing a carbon nanotube solution onto the dielectric, wherein self-assembly of the deposited carbon nanotubes within the trenches occurs based on i) attractive forces between the first charge on the surfaces of the carbon nanotubes and the second charge on the bottom surfaces of the trenches and ii) repulsive forces between the first charge on the surfaces of the carbon nanotubes and the first charge on sidewall and top surfaces of the trenches.

公开(公告)号：US20150194487A1

公开(公告)日：2015-07-09

申请号：US14664435

申请日：2015-03-20

Applicant: International Business Machines Corporation

Inventor： Sarunya Bangsaruntip ,  Guy Cohen ,  Michael A. Guillorn

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/775 ,  H01L29/165

CPC classification number: H01L29/0669 ,  B82Y10/00 ,  H01L21/28518 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78696

Abstract: Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.

Abstract translation: 提供了在纳米线FET器件中限定镶嵌栅极的技术。 一方面，提供一种制造FET器件的方法，包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 纳米线和焊盘以阶梯状构造在SOI层中图案化。 BOX凹入纳米线下方。 在凹入的BOX上形成可图案的电介质伪栅极，并围绕每个纳米线的一部分。 CMP停止层沉积在虚拟栅极和源极和漏极区域上。 在CMP停止层上沉积电介质膜。 使用CMP对电介质膜进行平面化以暴露虚拟栅极。 至少部分地去除虚拟栅极，以便在沟道区域中释放纳米线。 虚拟栅极被栅极导体材料代替。

公开(公告)号：US20130237039A1

公开(公告)日：2013-09-12

申请号：US13759648

申请日：2013-02-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey W. Sleight ,  Sarunya Bangsaruntip

IPC: H01L21/02

CPC classification number: H01L21/02104 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3247 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield.