公开(公告)号：US20210408287A1

公开(公告)日：2021-12-30

申请号：US17348267

申请日：2021-06-15

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Van der Plas

IPC: H01L29/78 ,  H01L27/092 ,  H01L23/48 ,  H01L21/8238

Abstract: Example embodiments relate to methods for inducing stress in semiconductor devices. One method includes a method for producing a first semiconductor device and a second semiconductor device configured to conduct current through the controlled density of charge carriers in a channel area. The charge carriers of the first semiconductor device have opposite polarity to the charge carriers of the second semiconductor device. The method includes producing a stress relaxed buffer (SRD) layer. The back side of the SRB layer is positioned on a substrate. The method also includes producing a semiconductor layer on the front side of the SRB layer. Additionally, the method includes producing the first semiconductor device and the second semiconductor device on the semiconductor layer, removing the substrate, thinning the SRB layer, producing a cavity in the SRB layer, and filling the cavity with a material to create a stress compensation area.

公开(公告)号：US11121086B2

公开(公告)日：2021-09-14

申请号：US16716262

申请日：2019-12-16

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van der Plas

IPC: H01L29/78 ,  H01L23/528 ,  H01L21/285 ,  H01L21/768 ,  H01L23/48 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H02M3/158

Abstract: A vertical isolated gate FET transistor integrated in the front end of line of a semiconductor chip is disclosed. In one aspect, the transistor includes a modified version of a buried power rail and back side TSV (through semiconductor via) connection for connecting the front end of line to a back side signal delivery network, such as a power delivery network (PDN), the PDN being arranged on the backside of the semiconductor substrate that carries the active devices of the FEOL on its front side. In contrast to standard power rail/TSV combinations, the TSV is not electrically connected to the rail, but isolated therefrom by a dielectric plug at the bottom of the rail. The TSV is isolated from the semiconductor substrate by a dielectric liner. Well regions are furthermore provided on the front side, enveloping the rail and the dielectric plug, and on the backside, surrounding the TSV and liner. On the back side, the well includes a contact area adjacent the TSV. The TSV thereby acts as the gate of the transistor, while the rail and the contact area respectively act as source and drain or vice versa.

公开(公告)号：US11114337B2

公开(公告)日：2021-09-07

申请号：US16716025

申请日：2019-12-16

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Julien Jussot ,  Geert Van der Plas

IPC: H01L21/768 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A method is provided for bonding and interconnecting two semiconductor chips arranged on semiconductor substrates. HSQ (Hydrogen Silsesquioxane) or an equivalent material is used as a bonding layer and after bonding and thinning one of the wafers (or first thinning and then bonding), the bond layer is locally irradiated by an e-beam through the thinned substrate, thereby locally transforming the bonding material into silicon oxide. Then a via opening is etched through the thinned substrate and an etch process selectively removes the oxide from an area delimited by the bonding material or vice versa. The filling of the via opening establishes an electrical connection between the bonded wafers, that is equivalent to a connection obtained by hybrid bonding, but that does not suffer from the disadvantages thereof.

公开(公告)号：US10712760B2

公开(公告)日：2020-07-14

申请号：US16452143

申请日：2019-06-25

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Bertrand Parvais

IPC: G05F1/595 ,  H01L29/76

Abstract: Example embodiments relate to low-temperature voltage references using Coulomb blockade mechanisms. One embodiment includes a method of generating a reference voltage. The method includes providing a first single-electron transistor (SET) and a second SET connected in series. The method also includes biasing the first SET and the second SET using a same biasing current (Ib). Further, the method includes operating the first SET at a slope of a first Coulomb peak and the second SET at a slope of a second Coulomb peak. The slope of the first Coulomb peak and the second Coulomb peak are of the same slope type selected from a rising slope, a peak maximum, and a falling slope. The second Coulomb peak is different from the first Coulomb peak. Additionally, the method includes generating the reference voltage (Vref) based on a difference between gate-to-source voltages of the first SET (Vgs1) and the second SET (Vgs2).

公开(公告)号：US20200006142A1

公开(公告)日：2020-01-02

申请号：US16456833

申请日：2019-06-28

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Stefaan Van Huylenbroeck ,  Geert Van der Plas

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/092 ,  H01L23/00

Abstract: A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.

公开(公告)号：US20250107199A1

公开(公告)日：2025-03-27

申请号：US18889130

申请日：2024-09-18

Applicant: Imec vzw

Inventor： Boon Teik Chan ,  Gaspard Hiblot ,  Gioele Mirabelli

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes forming an isolation structure in a substrate, forming a fin-shaped structure from the substrate, a bottom sacrificial layer, and a stack of layers, forming a dummy gate over a channel region of the fin-shaped structure, forming a recess at a source/drain region of the fin-shaped structure, the source/drain recess extending through the stack of layers and the bottom sacrificial layer, removing the bottom sacrificial layer thereby forming a void, depositing a bottom dielectric insulation layer in the void, extending the recess into the substrate, depositing a plug in the recess, forming an epitaxial structure to form a source/drain feature above the plug in the recess, removing the dummy gate, removing the sacrificial layers in the channel region, forming a replacement metal gate around the channel layers, thinning the substrate, etching the plug to expose the source/drain feature, and forming a source/drain electrical contact at the source/drain feature.

公开(公告)号：US20250096037A1

公开(公告)日：2025-03-20

申请号：US18889580

申请日：2024-09-19

Applicant: Imec vzw

Inventor： Gaspard Hiblot ,  Gioele Mirabelli

IPC: H01L21/768 ,  H01L29/66

Abstract: A method for forming a semiconductor device includes forming a trench for a buried interconnect structure between first and second fin structures and lining the trench with a dielectric layer. The method also includes etching a contact opening in a first portion of the dielectric layer adjacent a first region of the first fin structure while masking the second portion of the dielectric layer adjacent a second region of the second fin structure directly opposite the first region. The method also includes forming a local interconnect trench extending between the first and second regions, where the second portion of the dielectric layer partitions the local interconnect trench into first and second trench portions. The method also includes forming first and second local interconnects in the first and second trench portions. The first and second local interconnects are separated by the second portion of the dielectric layer.

公开(公告)号：US20240321889A1

公开(公告)日：2024-09-26

申请号：US18608650

申请日：2024-03-18

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Gioele Mirabelli

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: The disclosed technology generally relates to a complementary field effect transistor (CFET) cell. In one aspect, the CFET cell includes: a first transistor structure arranged in a first tier of the CFET cell; a second transistor structure arranged in a second tier of the CFET cell above the first tier; a set of top signal routing lines formed in a first metal layer above the second tier and connected to the first and the second transistor structures from above; and at least one bottom signal routing line formed in a second metal layer below the first tier and connected to the first transistor structure from below. The disclosed technology also generally relates to a method of fabricating a CFET cell.

公开(公告)号：US11757039B2

公开(公告)日：2023-09-12

申请号：US17348267

申请日：2021-06-15

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Van der Plas

IPC: H01L29/78 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/092

CPC classification number: H01L29/7849 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/481 ,  H01L27/0924

Abstract: Example embodiments relate to methods for inducing stress in semiconductor devices. One method includes a method for producing a first semiconductor device and a second semiconductor device configured to conduct current through the controlled density of charge carriers in a channel area. The charge carriers of the first semiconductor device have opposite polarity to the charge carriers of the second semiconductor device. The method includes producing a stress relaxed buffer (SRD) layer. The back side of the SRB layer is positioned on a substrate. The method also includes producing a semiconductor layer on the front side of the SRB layer. Additionally, the method includes producing the first semiconductor device and the second semiconductor device on the semiconductor layer, removing the substrate, thinning the SRB layer, producing a cavity in the SRB layer, and filling the cavity with a material to create a stress compensation area.

公开(公告)号：US20220270924A1

公开(公告)日：2022-08-25

申请号：US17669255

申请日：2022-02-10

Applicant: IMEC VZW

Inventor： Douglas Charles La Tulipe ,  Anne Jourdain ,  Gaspard Hiblot

IPC: H01L21/768 ,  H01L23/544

Abstract: The disclosed technology relates to methods for producing an interconnect structure on the back side of an integrated circuit chip. According to a first aspect, a via opening is etched in a top semiconductor layer, and filled with a sacrificial material, thereby forming a sacrificial pillar. Then front and back end of line portions are processed and the substrate is thinned. The etch stop layer and the sacrificial pillar are removed, and replaced an electrically conductive material forming a through semiconductor via. According to a second aspect, the sacrificial pillar is etched through the opening of a trench that intersects the pillar. Filling the trench with a conductive material also fills the cavity created by etching back the pillar resulting in an integral conductive pad and interconnect rail structure. The pillar can be removed and replaced by a conductive material, thereby creating the TSV connection.