公开(公告)号：US20230307499A1

公开(公告)日：2023-09-28

申请号：US18204635

申请日：2023-06-01

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Roman Baburske ,  Christian Jaeger ,  Johannes Georg Laven ,  Helmut Maeckel

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/1083 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/0869 ,  H01L29/7813 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397

Abstract: A power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.

公开(公告)号：US11682700B2

公开(公告)日：2023-06-20

申请号：US17208779

申请日：2021-03-22

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Roman Baburske ,  Christian Jaeger ,  Johannes Georg Laven ,  Helmut Maeckel

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/1083 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: An power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.

公开(公告)号：US11538906B2

公开(公告)日：2022-12-27

申请号：US17016472

申请日：2020-09-10

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Alexander Philippou ,  Christian Philipp Sandow

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/66 ,  H01L29/739

Abstract: A power device includes: a diode section; a semiconductor body; a drift region extending into the diode section; trenches in the diode section and extending along a vertical direction into the semiconductor body, two adjacent trenches defining a respective mesa portion in the semiconductor body; a body region in the mesa portions; in the diode section, a barrier region between the body and drift regions and having a dopant concentration at least 100 times greater than an average dopant concentration of the drift region and a dopant dose greater than that of the body region. The barrier region has a lateral structure according to which at least 50% of the body region in the diode section is coupled to the drift region at least by the barrier region, and at least 5% of the body region in the diode section is coupled to the drift region without the barrier region.

公开(公告)号：US20210313460A1

公开(公告)日：2021-10-07

申请号：US17350505

申请日：2021-06-17

Applicant: Infineon Technologies AG ,  Infineon Technologies Dresden GmbH & Co. KG

Inventor： Matteo Dainese ,  Alexander Philippou ,  Markus Beninger-Bina ,  Ingo Dirnstorfer ,  Erich Griebl ,  Christian Jaeger ,  Johannes Georg Laven ,  Caspar Leendertz ,  Frank Dieter Pfirsch

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

Abstract: A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

公开(公告)号：US20200006539A1

公开(公告)日：2020-01-02

申请号：US16566141

申请日：2019-09-10

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Christian Jaeger ,  Johannes Georg Laven ,  Antonio Vellei

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

Abstract: An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating.

公开(公告)号：US10439055B2

公开(公告)日：2019-10-08

申请号：US15940708

申请日：2018-03-29

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Christian Jaeger ,  Johannes Georg Laven ,  Antonio Vellei

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

Abstract: An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating.

公开(公告)号：US10424645B2

公开(公告)日：2019-09-24

申请号：US15657735

申请日：2017-07-24

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Erich Griebl ,  Johannes Georg Laven ,  Maria Cotorogea

IPC: H01L23/58 ,  H01L21/66 ,  H01L29/40 ,  H01L29/66 ,  H01L21/786 ,  H01L29/417 ,  H01L21/8234 ,  G01R31/02 ,  G01R31/26 ,  H01L23/522 ,  H01L29/739 ,  H01L29/78

Abstract: A semiconductor device includes a first source wiring substructure connected to a plurality of source doping region portions of a transistor structure, and a second source wiring substructure connected to a plurality of source field electrodes located in a plurality of source field trenches extending into a semiconductor substrate. A contact wiring portion of the first source wiring substructure and a contact wiring portion of the second source wiring substructure are located in a wiring layer of a layer stack located on the semiconductor substrate. The contact wiring portion of the first source wiring substructure and the contact wiring portion of the second source wiring substructure each have a lateral size sufficient for a contact for at least a temporary test measurement. The wiring layer including the contact wiring portions is located closer to the substrate than any ohmic electrical connection between the first and the second source wiring substructures.

公开(公告)号：US20190123185A1

公开(公告)日：2019-04-25

申请号：US16167926

申请日：2018-10-23

Applicant: Infineon Technologies AG

Inventor： Antonio Vellei ,  Markus Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Alexander Philippou ,  Francisco Javier Santos Rodriguez

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L21/225 ,  H01L21/324 ,  H01L21/265 ,  H01L29/423 ,  H01L21/033

Abstract: A method of processing a semiconductor device includes: providing a semiconductor body with a drift region; forming trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement having a lateral structure so that some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; subjecting the semiconductor body and the mask arrangement to a dopant material providing step to form a plurality of doping regions of a second conductivity type below bottoms of the exposed trenches; removing the mask arrangement; subjecting the semiconductor body to a temperature annealing step so that the doping regions extend in parallel to the first lateral direction and overlap to form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.

公开(公告)号：US20160099188A1

公开(公告)日：2016-04-07

申请号：US14861569

申请日：2015-09-22

Applicant: Infineon Technologies AG

Inventor： Christian Jaeger ,  Johannes Georg Laven ,  Frank Dieter Pfirsch ,  Alexander Philippou

IPC: H01L21/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L22/32 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7395 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7827

Abstract: A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region. The semiconductor device further includes: a first load contact structure included in the surface region and arranged for feeding a load current into the semiconductor body region; a first trench extending into the semiconductor body region and having a sensor electrode and a first dielectric, the first dielectric electrically insulating the sensor electrode from the second semiconductor region; an electrically conductive path electrically connecting the sensor electrode to the first semiconductor region; a first semiconductor path, wherein the first semiconductor region is electrically coupled to the first load contact structure by at least the first semiconductor path; a sensor contact structure included in the surface region and arranged for receiving an electrical potential of the sensor electrode.

Abstract translation: 半导体器件包括半导体本体区域和表面区域，该半导体本体区域包括第一导电型第一半导体区域型和第二导电型第二半导体区域。 所述半导体器件还包括：第一负载接触结构，包括在所述表面区域中并被布置成用于将负载电流馈送到所述半导体本体区域中; 延伸到半导体主体区域并具有传感器电极和第一电介质的第一沟槽，所述第一电介质将所述传感器电极与所述第二半导体区域电绝缘; 将传感器电极电连接到第一半导体区域的导电路径; 第一半导体路径，其中所述第一半导体区域通过至少所述第一半导体路径电耦合到所述第一负载接触结构; 传感器接触结构，包括在所述表面区域中并被布置成用于接收所述传感器电极的电位。

公开(公告)号：US20150279985A1

公开(公告)日：2015-10-01

申请号：US14228881

申请日：2014-03-28

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Johannes Georg Laven ,  Christian Jaeger ,  Frank Wolter ,  Frank Pfirsch ,  Antonio Vellei

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7841

Abstract: A transistor device includes a semiconductor mesa region between first and second trenches in a semiconductor body, a body region of a first conductivity type and a source region of a second conductivity type in the semiconductor mesa region, a drift region of the second conductivity type in the semiconductor body, and a gate electrode adjacent the body region in the first trench, and dielectrically insulated from the body region by a gate dielectric. The body region separates the source region from the drift region and extends to the surface of the semiconductor mesa region adjacent the source region. The body region comprises a surface region which adjoins the surface of the semiconductor mesa region and the first trench. The surface region has a higher doping concentration than a section of the body region that separates the source region from the drift region.

Abstract translation: 晶体管器件包括在半导体主体中的第一和第二沟槽之间的半导体台面区域，半导体台面区域中的第一导电类型的主体区域和第二导电类型的源极区域，第二导电类型的漂移区域 所述半导体本体和与所述第一沟槽中的所述主体区域相邻的栅电极，并且通过栅极电介质与所述体区电介质绝缘。 体区域将源极区域与漂移区域分离并延伸到与源极区域相邻的半导体台面区域的表面。 身体区域包括邻接半导体台面区域和第一沟槽的表面的表面区域。 表面区域具有比将源极区域与漂移区域分开的体区域的部分更高的掺杂浓度。