公开(公告)号：US20150179270A1

公开(公告)日：2015-06-25

申请号：US14641496

申请日：2015-03-09

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Nirschl

IPC: G11C16/14 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation.

Abstract translation: 实施例涉及包括多个非易失性存储器元件的系统和方法，其中至少两个非易失性存储器元件的集合共享一个选择元件，用于选择用于读取操作的非易失性存储器元件组中的特定一个的非易失性存储器元件之一， 一个程序操作。

公开(公告)号：US20150170762A1

公开(公告)日：2015-06-18

申请号：US14132053

申请日：2013-12-18

Applicant: Infineon Technologies AG

Inventor： Thomas Nirschl ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Thomas Kern ,  Thomas Liebermann

IPC: G11C29/02 ,  G06F11/10

CPC classification number: G11C29/024 ,  G06F11/1076

Abstract: The disclosure relates to systems and methods for performing a word line address scan in a semiconductor memory. More specifically, the disclosure provides a system and method for performing three scans for testing address decoder and word line drive circuits. The first scan determines whether only one word line is selected. The second scan determines whether the word line rise time to a target voltage level is within a specified time. Finally, the third scan determines whether the correct word line was selected. The present disclosure may realize all three scans or a combination of the three scans.

Abstract translation: 本公开涉及用于在半导体存储器中执行字线地址扫描的系统和方法。 更具体地，本公开提供了一种用于对地址解码器和字线驱动电路进行三次扫描的系统和方法。 第一次扫描确定是否只选择一个字线。 第二扫描确定到目标​​电压电平的字线上升时间是否在指定时间内。 最后，第三次扫描确定是否选择了正确的字线。 本公开可以实现所有三个扫描或三个扫描的组合。

公开(公告)号：US20150039805A1

公开(公告)日：2015-02-05

申请号：US13957604

申请日：2013-08-02

Applicant: Infineon Technologies AG

Inventor： Ulrich Backhausen ,  Thomas Kern ,  Thomas Nirschl ,  Jens Rosenbusch ,  Xiangting Bi ,  Edvin Paparisto

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F11/1048 ,  G06F12/0238 ,  G06F12/0292 ,  G06F2212/1032 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C2029/1806

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.

Abstract translation: 本公开涉及一种电子存储器系统，更具体地，涉及一种用于模拟电可擦除可编程只读存储器的系统，以及用于模拟电可擦除可编程只读存储器的方法。 根据本公开的实施例，提供了一种用于模拟电可擦除可编程只读存储器的系统，所述系统包括第一存储器部分和第二存储器部分，其中第一存储器部分包括多个存储位置，其被配置为存储 数据被分割成多个数据段，并且其中第二存储器部分被配置为存储将存储在第一存储器部分中的数据段的物理地址映射到数据段的逻辑地址的信息。

公开(公告)号：US20150007001A1

公开(公告)日：2015-01-01

申请号：US14327796

申请日：2014-07-10

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Ulrich Backhausen ,  Thomas Rabenalt ,  Michael Goessel ,  Klaus Oberlaender ,  Christian Badack

IPC: H03M13/15 ,  H03M13/00

CPC classification number: H03M13/151 ,  H03M13/152 ,  H03M13/155 ,  H03M13/1575 ,  H03M13/159 ,  H03M13/616 ,  H03M13/6575

Abstract: A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix.

Abstract translation: 一种电路，包括：校正子发生器，被配置为基于奇偶校验矩阵产生校正子，并且提供包括第一组位和第二组位的二进制字。 对于第一组位，奇偶校验矩阵提供第一组内的可校正位错误的纠错，对于第二组位，第二组中的可检测位错误的错误检测由奇偶校验矩阵 。

公开(公告)号：US20130346834A1

公开(公告)日：2013-12-26

申请号：US13975621

申请日：2013-08-26

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Ulrich Backhausen ,  Michael Goessel ,  Thomas Rabenalt ,  Stephane Lacouture

IPC: H03M13/15

CPC classification number: H03M13/151 ,  H03M13/152 ,  H03M13/155 ,  H03M13/1575 ,  H03M13/159 ,  H03M13/616 ,  H03M13/6575

Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.

Abstract translation: 用于校正编码比特序列中的至少一个比特误差的装置包括误差校正子发生器和比特误差校正器。 错误校正子发生器确定通过校验矩阵与编码比特序列的乘法导出的编码比特序列的错误校正。