公开(公告)号：US11848259B2

公开(公告)日：2023-12-19

申请号：US16219765

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/13 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/5381 ,  H01L24/00 ,  H01L25/0655 ,  H01L23/48 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/1703 ,  H01L2224/17133 ,  H01L2224/17177 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/153 ,  H01L2924/1517

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

公开(公告)号：US11676889B2

公开(公告)日：2023-06-13

申请号：US17573479

申请日：2022-01-11

Applicant: Intel Corporation

Inventor： Arnab Sarkar ,  Sujit Sharan ,  Dae-Woo Kim

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/49827 ,  H01L22/32 ,  H01L23/544 ,  H01L23/585 ,  H01L24/10 ,  H01L25/0655 ,  H01L24/16 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/14 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/3512

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US10418312B2

公开(公告)日：2019-09-17

申请号：US15749465

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Arnab Sarkar ,  Sujit Sharan ,  Dae-Woo Kim

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US10283453B2

公开(公告)日：2019-05-07

申请号：US15297005

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim

IPC: H01L21/768 ,  H01L23/538 ,  G06F17/50 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

公开(公告)号：US20170040264A1

公开(公告)日：2017-02-09

申请号：US15297005

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5381 ,  G06F17/5077 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及互连路由配置和相关技术。 在一个实施例中，一种装置包括基板，设置在基板上并具有第一多个迹线的第一布线层和与第一布线层直接相邻设置且具有第二多个迹线的第二布线层，其中第一布线层 第一多个迹线的迹线具有大于第二多个迹线的第二迹线的宽度的宽度。 可以描述和/或要求保护其他实施例。