公开(公告)号：US20200066855A1

公开(公告)日：2020-02-27

申请号：US16074373

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Glenn A. GLASS ,  Harold W. KENNEL ,  Anand S. MURTHY ,  Willy RACHMADY ,  Gilbert DEWEY ,  Sean T. MA ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/201

Abstract: An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material.

公开(公告)号：US20180145077A1

公开(公告)日：2018-05-24

申请号：US15574820

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Anand S. MURTHY ,  Tahir GHANI ,  Willy RACHMADY ,  Chandra S. MOHAPATRA ,  Jack T. KAVALIEROS ,  Glenn A. GLASS

IPC: H01L27/092 ,  H01L29/205 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/8258 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

公开(公告)号：US20240347610A1

公开(公告)日：2024-10-17

申请号：US18757013

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Koustav GANGULY ,  Ryan KEECH ,  Subrina RAFIQUE ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Ehren MANNEBACH ,  Mauro KOBRINSKY ,  Gilbert DEWEY

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28556 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/41766 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

公开(公告)号：US20240290789A1

公开(公告)日：2024-08-29

申请号：US18654855

申请日：2024-05-03

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Anand S. MURTHY

IPC: H01L27/092 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

公开(公告)号：US20220093790A1

公开(公告)日：2022-03-24

申请号：US17030221

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Anand S. MURTHY ,  Robert EHLERT ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Sandrine CHARUE-BAKKER

IPC: H01L29/78 ,  H01L29/20 ,  H01L27/092 ,  H01L29/205 ,  H01L29/40

Abstract: Co-integrated gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuit technology is described. In an example, a semiconductor structure includes a silicon (111) substrate having a first region and a second region. A structure including gallium and nitrogen is on the first region of the silicon (111) substrate, the structure including gallium and nitrogen having a top surface. A structure including germanium is on the second region of the silicon (111) substrate, the structure including germanium having a top surface co-planar with the top surface of the structure including gallium and nitrogen. A dielectric spacer is laterally between and in contact with the structure including gallium and nitrogen and the structure including germanium, the dielectric spacer on the silicon (111) substrate.

公开(公告)号：US20220093590A1

公开(公告)日：2022-03-24

申请号：US17026052

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Zachary GEIGER ,  Glenn A. GLASS ,  Szuya S. LIAO

IPC: H01L27/088 ,  H01L29/423

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure is in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：US20220028747A1

公开(公告)日：2022-01-27

申请号：US17495696

申请日：2021-10-06

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Daniel B. AUBERTINE ,  Anand S. MURTHY ,  Gaurav THAREJA ,  Tahir GHANI

IPC: H01L21/8238 ,  H01L29/10 ,  H01L21/8258

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

公开(公告)号：US20200287011A1

公开(公告)日：2020-09-10

申请号：US16881541

申请日：2020-05-22

Applicant: INTEL CORPORATION

Inventor： Glenn A. GLASS ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L21/285 ,  H01L21/768

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

公开(公告)号：US20190035926A1

公开(公告)日：2019-01-31

申请号：US16070207

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Karthik JAMBUNATHAN

IPC: H01L29/78 ,  H01L21/764 ,  H01L29/66 ,  H01L29/10

Abstract: A replacement fin layer is deposited on a sub-fin layer in trenches isolated by an insulating layer on a substrate. The replacement fin layer has first component rich side portions and a second component rich core portion. The second component rich core portion is etched to generate a double fin structure comprising the first component rich fins.

公开(公告)号：US20190019891A1

公开(公告)日：2019-01-17

申请号：US16070262

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Anand S. MURTHY ,  Karthik JAMBUNATHAN ,  Chandra S. MOHAPATRA ,  Hei KAM ,  Nabil G. MISTKAWI ,  Jun Sung KANG ,  Biswajeet GUHA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/423

Abstract: A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.