公开(公告)号：US20250004966A1

公开(公告)日：2025-01-02

申请号：US18345748

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Huimin Chen ,  James Akiyama ,  John Howard ,  Venkataramani Gopalakrishnan ,  Nirmala Bailur

IPC: G06F13/38 ,  G06F13/40

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to route display stream data. An example system disclosed herein to route display stream data includes a circuit board comprising decoding circuitry to decode Peripheral Component Interconnect Express (PCIe) data packets into a display port stream data, the PCIe data packets encoded by a discrete graphics circuitry, and a Universal Serial Bus (USB) connector on the circuit board coupled to the decoding circuitry, wherein the USB connector is to output the display port stream data.

公开(公告)号：US20250004222A1

公开(公告)日：2025-01-02

申请号：US18345044

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Debabani Choudhury ,  Huimin Chen ,  Eric Gantner ,  Stephen Hall ,  Cooper Levy ,  Shawn Mceuen ,  Luis Paniagua Acuna ,  Peter Sagazio ,  Harry Skinner ,  Kerry Stevens ,  Ana Yepes

IPC: G02B6/42 ,  G02B6/44

Abstract: A rotatable circular waveguide structure is described that may comprise circular waveguide sections configured to propagate electromagnetic radiation. The circular waveguide sections may enable data signals to be transmitted between portions of an electronic device, such as a chassis and display portion, which may be rotatable with respect to one another. The rotatable circular waveguide structure may comprise one or more circular waveguide sections that are routed through a hinge of the electronic device, as well as one or more rotatable junctions. The rotatable junctions enable a rotation of circular waveguide sections with respect to one another as the coupled portions of the electronic device are also rotated. The rotatable circular waveguide structure may replace the use of data cables that are conventionally used to carry data signals between portions of an electronic device.

公开(公告)号：US20230385218A1

公开(公告)日：2023-11-30

申请号：US17826933

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Udaya Natarajan ,  Kannappan Rajaraman ,  Huimin Chen

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/382 ,  G06F13/4282 ,  G06F2213/0042 ,  G06F2213/3812

Abstract: Embodiments herein relate to a universal serial bus (USB) host system that is configured to perform port orientation identification and/or configuration lane identification. Specifically, the USB host system may include a USB Type-C port configured to communicate in accordance with the USB 3.2 protocol. The described identifications may be performed without the use of a power delivery (PD) and/or Type-C port controller (TCPC) module. Other embodiments may be described and claimed.

公开(公告)号：US20230076468A1

公开(公告)日：2023-03-09

申请号：US17468179

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Huimin Chen ,  Selvakumar Panneer ,  Zhengmin Li

IPC: G06F9/445 ,  G06F13/20 ,  G06F9/4401

Abstract: A method includes receiving a request for a transfer of data on a bus of a computing device; determining a direction for the transfer, at least in part based on the request; determining a quantity of data for the transfer, at least in part based on the request; determining a power state for a lane of the bus, at least in part based on the direction and the quantity of data for the transfer; and setting the power state for the lane of the bus.

公开(公告)号：US11347580B2

公开(公告)日：2022-05-31

申请号：US17229162

申请日：2021-04-13

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Andrew Martwick ,  Howard Heck ,  Robert Dunstan ,  Dennis Bell ,  Abdul Ismail

IPC: H03M5/06 ,  G06F11/10 ,  H03M5/12

Abstract: Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.

公开(公告)号：US20190340146A1

公开(公告)日：2019-11-07

申请号：US16513691

申请日：2019-07-16

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Jingbo Li ,  Kai Xiao ,  Yong Yang ,  Chunfei Ye

IPC: G06F13/40 ,  G06F1/3234 ,  H03K5/24 ,  G06F5/06 ,  H04L12/40

Abstract: An apparatus, such as a re-driver, can include a receiver port coupled to a first link partner across a first link; a transmitter port coupled to a second link partner across a second link; and a power management (PM) controller implemented in hardware. The PM controller can detect a PM control signal, determine a PM state for the apparatus based on the PM control signal, and cause the apparatus to enter the PM state. The apparatus can transmit electrical signals to the second link partner based on the PM state. The PM management control signal can include a clock request, an electrical idle, a common mode voltage, or other electrical signal indicative of a PM link state change of a link partner coupled to the re-driver.

公开(公告)号：US10127187B2

公开(公告)日：2018-11-13

申请号：US15607367

申请日：2017-05-26

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Duane G. Quiet

IPC: G06F13/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

公开(公告)号：US09875210B2

公开(公告)日：2018-01-23

申请号：US14317874

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Howard L. Heck

IPC: H04B10/29 ,  G06F13/42 ,  H04B3/58

CPC classification number: G06F13/423 ,  G05B2219/25181 ,  G06F13/4045 ,  G06F13/4256 ,  G06F2213/0052 ,  H04B3/58 ,  H04B10/29 ,  H04B2203/5479 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer, wherein an algorithm is to enable the at least one retimer to announce its presence by asserting a bit of a presence message during link initialization. The at least one retimer can declare an index and is accessible via the index.

公开(公告)号：US09794055B2

公开(公告)日：2017-10-17

申请号：US15073298

申请日：2016-03-17

Applicant: Intel Corporation

Inventor： Huimin Chen

IPC: H04L27/00 ,  H04L7/00

CPC classification number: H04L7/0008 ,  G06F13/40 ,  H04L7/0016 ,  H04L25/14

Abstract: A source component includes a clock source to generate a clock signal, a plurality of front-end driver circuits to transmit signals to a sink component over a plurality of data lanes of an interconnect, and a clock distribution circuit coupled to the clock source and the plurality of front-end driver circuits. The clock distribution circuit is to distribute a first clock pulse of the clock signal on a first data lane and a second clock pulse of the clock signal on a second data lane. A sink component is to recover the first clock pulse of the clock signal from the first data lane and the second clock pulse of the clock signal from the second data lane, wherein the clock recovery circuit includes clock reconstruction logic to reconstruct the clock signal from the first clock pulse and the second clock pulse.

公开(公告)号：US09559905B2

公开(公告)日：2017-01-31

申请号：US14582597

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Karthi R. Vadivelu ,  Howard L. Heck

IPC: H04L12/24 ,  H04W52/28 ,  H04L12/12

CPC classification number: H04L41/0816 ,  H04L12/12

Abstract: An apparatus for retimer configuration and control is described herein. The apparatus includes at least one retimer. The is to receive an inband low frequency periodic signal (LFPS), and to send an inband LFPS based pulse width modulation message (LBPM) in response to the inband LFPS. The retimer is configured by decoding the LBPM.

Abstract translation: 本文描述了重新定时器配置和控制的装置。 该装置包括至少一个重定时器。 接收带内低频周期信号（LFPS），并响应于带内LFPS发送基于带宽LFPS的脉宽调制消息（LBPM）。 重定时器通过对LBPM进行解码来配置。