公开(公告)号：US20150249131A1

公开(公告)日：2015-09-03

申请号：US14707292

申请日：2015-05-08

Applicant: Intel Corporation

Inventor： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITIKA GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

IPC: H01L29/10 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

Abstract translation: 本发明的实施例包括外延层，其以允许该层以两个或三个自由度放松的方式直接接触例如纳米线，翅片或支柱。 外延层可以包括在晶体管的沟道区中。 可以去除纳米线，鳍或柱以提供对外延层的更大的访问。 这样做可以允许围绕外延层的顶部，底部和侧壁的“全向栅极”结构。 本文描述了其它实施例。

公开(公告)号：US20210118983A1

公开(公告)日：2021-04-22

申请号：US17116297

申请日：2020-12-09

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

IPC: H01L49/02 ,  H01L23/522

Abstract: Techniques are disclosed for forming an integrated circuit including a capacitor having a multilayer dielectric stack. For example, the capacitor may be a metal-insulator-metal capacitor (MIMcap), where the stack of dielectric layers is used for the insulator or ‘I’ portion of the MIM structure. In some cases, the composite or multilayer stack for the insulator portion of the MIM structure may include a first oxide layer, a dielectric layer, a second oxide layer, and a high-k dielectric layer, as will be apparent in light of this disclosure. Further, the multilayer dielectric stack may include an additional high-k dielectric layer, for example. Use of such multilayer dielectric stacks can enable increases in capacitance density and/or breakdown voltage for a MIMcap device. Further, use of a multilayer dielectric stack can enable tuning of the breakdown and capacitance characteristics as desired. Other embodiments may be described and/or disclosed.

公开(公告)号：US20200321445A1

公开(公告)日：2020-10-08

申请号：US16907445

申请日：2020-06-22

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

IPC: H01L29/51 ,  H01L29/20 ,  H01L29/778 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed herein for ferroelectric-based field-effect transistors (FETs) with threshold voltage (VT) switching for enhanced RF switch transistor on-state and off-state performance. Employing a ferroelectric gate dielectric layer that can switch between two ferroelectric states enables a higher VT during the transistor off-state (VT,hi) and a lower VT during the transistor on-state (VT,lo). Accordingly, the transistor on-state resistance (Ron) can be maintained low due to the available relatively high gate overdrive (Vg,on−VT,lo) while still handling a relatively high maximum RF power in the transistor off-state due to the high VT,hi −Vg,off value. Thus, the Ron of an RF switch transistor can be improved without sacrificing maximum RF power, and/or vice versa, the maximum RF power can be improved without sacrificing the Ron. A ferroelectric layer (e.g., including HfxZryO) can be formed between a transistor gate dielectric layer and gate electrode to achieve such benefits.

公开(公告)号：US20200295166A1

公开(公告)日：2020-09-17

申请号：US16326594

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  PAUL B. FISCHER

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66 ,  H01L21/762

Abstract: Techniques are disclosed for forming a heterojunction bipolar transistor (HBT) that includes a laterally grown epitaxial (LEO) base layer that is disposed between corresponding emitter and collector layers. Laterally growing the base layer of the HBT improves electrical and physical contact between electrical contacts to associated portions of the HBT device (e.g., a collector). By improving the quality of electrical and physical contact between a layer of an HBT device and corresponding electrical contacts, integrated circuits using HBTs are better able to operate at gigahertz frequency switching rates used for modern wireless communications.

公开(公告)号：US20190173452A1

公开(公告)日：2019-06-06

申请号：US16323665

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： BRUCE A. BLOCK ,  SANSAPTAK DASGUPTA ,  PAUL B. FISCHER ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

IPC: H03H9/56 ,  H03H3/02 ,  H03H9/02 ,  H03H9/13 ,  H03H9/17

Abstract: Techniques are disclosed for forming resonator devices using epitaxially grown piezoelectric films. Given the epitaxy, the films are single crystal or monocrystalline. In some cases, the piezoelectric layer of the resonator device may be an epitaxial III-V layer such as an Aluminum Nitride, Gallium Nitride, or other group III material-nitride (III-N) compound film grown as a part of a single crystal III-V material stack. In an embodiment, the III-V material stack includes, for example, a single crystal AlN layer and a single crystal GaN layer, although any other suitable single crystal piezoelectric materials can be used. An interdigitated transducer (IDT) electrode is provisioned on the piezoelectric layer and defines the operating frequency of the filter. A plurality of the resonator devices can be used to enable filtering specific different frequencies on the same substrate (by varying dimensions of the IDT electrodes).

公开(公告)号：US20190058049A1

公开(公告)日：2019-02-21

申请号：US16080822

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/516 ,  H01L28/00 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/6684 ,  H01L29/7786 ,  H01L29/78391

Abstract: Techniques are disclosed herein for ferroelectric-based field-effect transistors (FETs) with threshold voltage (VT) switching for enhanced RF switch transistor on-state and off-state performance. Employing a ferroelectric gate dielectric layer that can switch between two ferroelectric states enables a higher VT during the transistor off-state (VT,hi) and a lower VT during the transistor on-state (VT,lo). Accordingly, the transistor on-state resistance (Ron) can be maintained low due to the available relatively high gate overdrive (Vg,on−VT,lo) while still handling a relatively high maximum RF power in the transistor off-state due to the high VT,hi−Vg,off value. Thus, the Ron of an RF switch transistor can be improved without sacrificing maximum RF power, and/or vice versa, the maximum RF power can be improved without sacrificing the Ron. A ferroelectric layer (e.g., including HfxZryO) can be formed between a transistor gate dielectric layer and gate electrode to achieve such benefits.

公开(公告)号：US20190058042A1

公开(公告)日：2019-02-21

申请号：US16080100

申请日：2016-03-30

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  SANAZ K. GARDNER ,  SEUNG HOON SUNG

IPC: H01L29/20 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778

Abstract: Techniques are disclosed for forming transistors including retracted raised source/drain (S/D) to reduce parasitic capacitance. In some cases, the techniques include forming ledges for S/D epitaxial regrowth on a high-quality crystal nucleation surface. The techniques may also include forming the raised sections of the S/D regions (e.g., the portions adjacent to spacer material between the S/D regions and the gate material) in a manner such that the S/D raised sections are retracted from the gate material. This can be achieved by forming a notch at the interface between a polarization charge inducing layer and an oxide layer using a wet etch process, such that a relatively high-quality surface of the polarization charge inducing layer material is exposed for S/D regrowth. Therefore, the benefits derived from growing the S/D material from a high-quality nucleation surface can be retained while reducing the parasitic overlap capacitance penalty that would otherwise be present.

公开(公告)号：US20180342985A1

公开(公告)日：2018-11-29

申请号：US15777744

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  SEUNG HOON SUNG ,  SANAZ K. GARDNER

IPC: H03F1/02 ,  H03F3/195 ,  H03F3/213 ,  H01L29/20 ,  H01L29/205 ,  H01L29/49 ,  H01L29/51 ,  H01L29/778 ,  H01L23/66

CPC classification number: H03F1/0222 ,  H01L23/66 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7786 ,  H01L29/7787 ,  H03F3/193 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/102 ,  H03F2200/105 ,  H03F2200/15 ,  H03F2200/18 ,  H03F2200/451

Abstract: Envelope-tracking control techniques are disclosed for highly-efficient radio frequency (RF) power amplifiers. In some cases, a III-V semiconductor material (e.g., GaN or other group III material-nitride (III-N) compounds) MOSFET including a high-k gate dielectric may be used to achieve such highly-efficient RF power amplifiers. The use of a high-k gate dielectric can help to ensure low gate leakage and provide high input impedance for RF power amplifiers. Such high input impedance enables the use of envelope-tracking control techniques that include gate voltage (Vg) modulation of the III-V MOSFET used for the RF power amplifier. In such cases, being able to modulate Vg of the RF power amplifier using, for example, a voltage regulator, can result in double-digit percentage gains in power-added efficiency (PAE). In some instances, the techniques may simultaneously utilize envelope-tracking control techniques that include drain voltage (Vd) modulation of the III-V MOSFET used for the RF power amplifier.

公开(公告)号：US20180323767A1

公开(公告)日：2018-11-08

申请号：US15773016

申请日：2015-12-04

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

IPC: H03H9/17 ,  H03H9/13 ,  H03H9/56 ,  H03H3/02 ,  H03H9/02

CPC classification number: H03H9/173 ,  H03H3/02 ,  H03H9/02015 ,  H03H9/13 ,  H03H9/174 ,  H03H9/562 ,  H03H2003/021 ,  H03H2003/023

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices using epitaxially grown piezoelectric films. In some cases, the piezoelectric layer of the FBAR may be an epitaxial III-V layer such as an aluminum nitride (AlN) or other group III material-nitride (III-N) compound film grown as a part of a III-V material stack, although any other suitable piezoelectric materials can be used. Use of an epitaxial piezoelectric layer in an FBAR device provides numerous benefits, such as being able to achieve films that are thinner and higher quality compared to sputtered films, for example. The higher quality piezoelectric film results in higher piezoelectric coupling coefficients, which leads to higher Q-factor of RF filters including such FBAR devices. Therefore, the FBAR devices can be included in RF filters to enable filtering high frequencies of greater than 3 GHz, which can be used for 5G wireless standards, for example.

公开(公告)号：US20180175184A1

公开(公告)日：2018-06-21

申请号：US15576508

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  SANAZ K. GARDNER ,  MARKO RADOSAVLJEVIC ,  SEUNG HOON SUNG ,  ROBERT S. CHAU

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L21/76248 ,  H01L29/2003 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78681

Abstract: Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor structures can be used for system-on-chip integration of high-voltage GaN front-end radio frequency (RF) switches on a bulk silicon substrate. The techniques can include, for example, forming multiple fins in a substrate, depositing the GaN layer on the fins, oxidizing at least a portion of each fin in a gap below the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. The techniques can be used to form various non-planar isolated GaN transistor architectures having a relatively small form factor, low on-state resistance, and low off-state leakage, in some cases.