公开(公告)号：US20180323106A1

公开(公告)日：2018-11-08

申请号：US15774446

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC ,  SANAZ GARDNER ,  SEUNG HOON SUNG

IPC: H01L21/8258 ,  H01L27/06 ,  H01L27/085

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7786

Abstract: Techniques are disclosed for fabricating co-planar p-channel and n-channel gallium nitride (GaN)-based transistors on silicon (Si). In accordance with some embodiments, a Si substrate may be patterned with recessed trenches located under corresponding openings formed in a dielectric layer over the substrate. Within each recessed trench, a stack including a buffer layer, a GaN or indium gallium nitride (InGaN) layer, and a polarization layer may be selectively formed, in accordance with some embodiments. The p-channel stack further may include another GaN or InGaN layer over its polarization layer, with source/drain (S/D) portions adjacent the m-plane or a-plane sidewalls of that GaN or InGaN layer. The n-channel may include S/D portions over its GaN or InGaN layer, within its polarization layer, in accordance with some embodiments. Gate stack placement can be customized to provide any desired combination of enhancement and depletion modes for the resultant neighboring p-channel and n-channel transistor devices.

公开(公告)号：US20170358645A1

公开(公告)日：2017-12-14

申请号：US15525269

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SANAZ K. GARDNER ,  MARKO RADOSAVLJEVIC ,  GLENN A. GLASS

IPC: H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/775 ,  H01L21/306 ,  H01L21/02 ,  H01L29/20 ,  H01L29/161 ,  H01L29/04

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7605 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/122 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

公开(公告)号：US20170125524A1

公开(公告)日：2017-05-04

申请号：US15405182

申请日：2017-01-12

Applicant: Intel Corporation

Inventor： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/20 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

公开(公告)号：US20160197173A1

公开(公告)日：2016-07-07

申请号：US14912887

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  MARKO RADOSAVLJEVIC ,  RAVI PILLARISETTY ,  MATTHEW V. METZ

IPC: H01L29/775 ,  H01L29/15 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/205

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/155 ,  H01L29/205 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66469 ,  H01L29/78681 ,  H01L29/78696

Abstract: Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

Abstract translation: 描述具有III-V族材料活性区域和渐变栅极电介质的半导体器件及其制造方法。 在一个示例中，半导体器件包括设置在衬底上方的III-V族材料沟道区。 栅极叠层设置在III-V族材料沟道区上。 栅堆叠包括直接设置在III-V材料沟道区和栅电极之间的渐变高k栅介质层。 渐变的高k栅极电介质层在III-V材料沟道区附近具有较低的介电常数，并且在栅电极附近具有更高的介电常数。 源极/漏极区域设置在栅极堆叠的两侧。

公开(公告)号：US20200313649A1

公开(公告)日：2020-10-01

申请号：US16882992

申请日：2020-05-26

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

IPC: H03H9/17 ,  H03H3/02 ,  H03H9/02 ,  H03H9/13 ,  H03H9/56

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices using epitaxially grown piezoelectric films. In some cases, the piezoelectric layer of the FBAR may be an epitaxial III-V layer such as an aluminum nitride (AlN) or other group III material-nitride (III-N) compound film grown as a part of a III-V material stack, although any other suitable piezoelectric materials can be used. Use of an epitaxial piezoelectric layer in an FBAR device provides numerous benefits, such as being able to achieve films that are thinner and higher quality compared to sputtered films, for example. The higher quality piezoelectric film results in higher piezoelectric coupling coefficients, which leads to higher Q-factor of RF filters including such FBAR devices. Therefore, the FBAR devices can be included in RF filters to enable filtering high frequencies of greater than 3 GHz, which can be used for 5G wireless standards, for example.

公开(公告)号：US20200219772A1

公开(公告)日：2020-07-09

申请号：US16239059

申请日：2019-01-03

Applicant: INTEL CORPORATION

Inventor： RAHUL RAMASWAMY ,  NIDHI NIDHI ,  WALID M. HAFEZ ,  JOHANN C. RODE ,  PAUL FISCHER ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC ,  SANSAPTAK DASGUPTA

IPC: H01L21/8252 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/872 ,  H01L29/66

Abstract: An integrated circuit structure and methodologies of forming same. In an embodiment, the integrated circuit structure includes a transistor gate structure in a first region of semiconductor material and a diode in a second region of the semiconductor material. The gate structure has a gate electrode of conductive material with a liner along sides and a bottom of the gate electrode. The gate electrode has a gate length less than a threshold dimension value. The diode includes a body of the conductive material in contact with the semiconductor material and includes the liner along sides of the body of conductive material. The body of conductive material has a lateral dimension greater than the threshold dimension value. The liner can include, for example, a gate dielectric and a diffusion barrier in some embodiments. In other embodiments, the liner is the gate dielectric (without any diffusion barrier).

公开(公告)号：US20200119030A1

公开(公告)日：2020-04-16

申请号：US16303485

申请日：2016-06-30

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  PRASHANT MAJHI ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

IPC: H01L27/11556 ,  H01L29/08 ,  H01L29/20 ,  H01L29/788 ,  H01L29/36 ,  H01L29/423 ,  H01L29/205 ,  H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213

Abstract: Techniques are disclosed for forming three-dimensional (3D) NAND structures including group III-nitride (III-N) material channels. Typically, polycrystalline silicon (poly-Si) channels are used for 3D NAND structures, such as 3D NAND flash memory devices. However, using III-N channel material for 3D NAND structures offers numerous benefits over poly-Si channel material, such as relatively lower resistance in the channel, relatively higher current densities, and relatively lower leakage. Therefore, using III-N channel material enables an increased number of floating gates or storage cells to be stacked in 3D NAND structures, thereby leading to increased capacity for a given integrated circuit footprint (e.g., increased GB/cm2). For instance, use of III-N channel material can enable greater than 100 floating gates for a 3D NAND structure. Other embodiments may be described and/or disclosed.

公开(公告)号：US20190229705A1

公开(公告)日：2019-07-25

申请号：US16326590

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  PAUL B. FISCHER ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

IPC: H03H9/205 ,  H01L27/20 ,  H01L41/187 ,  H01L41/08 ,  H03H3/02 ,  H01L41/316 ,  H01L41/29 ,  H03H9/58 ,  H03H9/60 ,  H03H9/02

Abstract: An integrated circuit film bulk acoustic resonator (FBAR) device having multiple resonator thicknesses is formed on a common substrate in a stacked configuration. In an embodiment, a seed layer is deposited on a substrate, and one or more multi-layer stacks are deposited on the seed layer, each multi-layer stack having a first metal layer deposited on a first sacrificial layer, and a second metal layer deposited on a second sacrificial layer. The second sacrificial layer can be removed and the resulting space is filled in with a piezoelectric material, and the first sacrificial layer can be removed to release the piezoelectric material from the substrate and suspend the piezoelectric material above the substrate. More than one multi-layer stack can be added, each having a unique resonant frequency. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate.

公开(公告)号：US20180331156A1

公开(公告)日：2018-11-15

申请号：US15777511

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

IPC: H01L27/20 ,  H03H9/17 ,  H03H9/56 ,  H01L27/06 ,  H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H03H3/02 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8258 ,  H01L41/187 ,  H01L41/314 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L27/20 ,  H01L21/0254 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0617 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/7787 ,  H01L41/187 ,  H01L41/314 ,  H03H3/02 ,  H03H9/0542 ,  H03H9/173 ,  H03H9/562 ,  H03H9/564 ,  H03H2003/021

Abstract: Techniques are disclosed for forming a monolithic integrated circuit semiconductor structure that includes a radio frequency (RF) frontend portion and may further include a CMOS portion. The RF frontend portion includes componentry implemented with column III-N semiconductor materials such as gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and compounds thereof, and the CMOS portion includes CMOS logic componentry implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). Either of the CMOS or RF frontend portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of III-N transistors and/or RF filters, along with column IV CMOS devices on a single substrate. In a more general sense, the techniques can be used for SoC integration of an RF frontend having diverse III-N componentry on a single substrate, in accordance with some embodiments.

公开(公告)号：US20180047839A1

公开(公告)日：2018-02-15

申请号：US15790907

申请日：2017-10-23

Applicant: INTEL CORPORATION

Inventor： RAVI PILLARISETTY ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  UDAY SHAH ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  NILOY MUKHERJEE ,  GILBERT DEWEY ,  BEEN Y. JIN ,  ROBERT S. CHAU

IPC: H01L29/775 ,  B82Y10/00 ,  H01L29/778 ,  H01L29/66 ,  H01L29/267 ,  H01L29/15 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/76 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.