公开(公告)号：US07983181B1

公开(公告)日：2011-07-19

申请号：US11379866

申请日：2006-04-24

申请人： Paul Miranda ,  Larry D. Hewitt

发明人： Paul Miranda ,  Larry D. Hewitt

IPC分类号： H04L12/26

CPC分类号： H03M13/09 ,  H04L1/0061 ,  H04L25/14

摘要： A technique for negotiating the width of a link between a first device and a second device includes detecting, during initialization, a respective signal on one or more control lines associated with at least a portion of an N-bit link. The N-bit link is configured as a single link having a width of N or multiple sublinks having a width less than N based on a respective value of the respective signal on the one or more control lines.

摘要翻译： 用于协商第一设备和第二设备之间的链路的宽度的技术包括在初始化期间检测与N位链路的至少一部分相关联的一个或多个控制线上的相应信号。 基于一个或多个控制线上的相应信号的相应值，将N位链路配置为宽度为N的单个链路或宽度小于N的多个子链路。

公开(公告)号：US06725297B1

公开(公告)日：2004-04-20

申请号：US10093146

申请日：2002-03-07

申请人： Tahsin Askar ,  Larry D. Hewitt ,  Eric G. Chambers

发明人： Tahsin Askar ,  Larry D. Hewitt ,  Eric G. Chambers

IPC分类号： G06F1300

CPC分类号： G06F13/128

摘要： A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.

摘要翻译： 用于计算机系统的I / O节点的外围接口电路。 一种用于计算机系统的输入/输出节点的外围接口电路包括第一缓冲电路，第二缓冲电路和总线接口电路。 第一缓冲电路接收分组命令，并且可以包括每个对应于多个虚拟通道的相应虚拟通道的第一多个缓冲器。 第二缓冲电路被耦合以从总线接口电路接收分组命令，并且可以包括每个对应于多个虚拟通道中的相应虚拟通道的第二多个缓冲器。 总线接口电路可以被配置为将存储在第一缓冲器电路中的选择的分组命令转换成适合于在外围总线上传输的命令。

公开(公告)号：US06202116B1

公开(公告)日：2001-03-13

申请号：US09098876

申请日：1998-06-17

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： G06F1300

CPC分类号： G06F13/4273

摘要： A data bus is divided into two portions. One portion of the bus transfers data from one side of the bus to the other and the other portion of the bus transfers data in the opposite direction. Bus cycles that originate from one side of the bus only go in one direction (from the originator to the other side). In order to avoid inefficiency because one of the portions of the bus may become unused if a long bus cycle is going in one direction while nothing is being transferred in the opposite direction, one side can take over the whole data bus and transfer data over both sides of the bus.

摘要翻译： 数据总线分为两部分。 总线的一部分将数据从总线的一侧传输到另一侧，而总线的另一部分以相反的方向传输数据。 从总线一侧起始的总线循环只能沿一个方向（从始发者到另一方）。 为了避免低效率，因为如果长的总线周期在一个方向上进行而总线周期不会在相反的方向上传输，总线的一部分可能会变得不用，则一侧可以接管整个数据总线并且通过两者传输数据 公车两边。

公开(公告)号：US06862647B1

公开(公告)日：2005-03-01

申请号：US10059691

申请日：2002-01-29

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： G06F1/00 ,  G06F11/267

CPC分类号： G06F11/221

摘要： A system and method for observing transactions on a packet bus is disclosed. In one embodiment, a computer system includes a plurality of input/output (I/O) nodes serially coupled to a processor. Each of the I/O nodes may be configured to operate in a first (normal) mode, and a second (analysis) mode. During the normal mode, packets may be selectively conveyed through an I/O tunnel in the I/O node, and particular packets may be selectively conveyed to a peripheral bus interface in the I/O node. In the analysis mode, electrical signals corresponding to packets conveyed through the I/O tunnel may be replicated on a peripheral bus coupled to the peripheral bus interface. No conversion from the packet bus protocol to the peripheral bus protocol. A signal analyzer may be coupled to the peripheral bus, thereby allowing observation of the electrical signals.

摘要翻译： 公开了一种用于观察分组总线上的事务的系统和方法。 在一个实施例中，计算机系统包括串行耦合到处理器的多个输入/输出（I / O）节点。 每个I / O节点可以被配置为以第一（正常）模式和第二（分析）模式操作。 在正常模式期间，可以通过I / O节点中的I / O隧道选择性地传送分组，并且可以将特定分组选择性地传送到I / O节点中的外围总线接口。 在分析模式中，对应于通过I / O隧道传送的分组的电信号可以在耦合到外围总线接口的外围总线上复制。 无需从分组总线协议转换为外设总线协议。 信号分析器可以耦合到外围总线，从而允许观察电信号。

公开(公告)号：US06807599B2

公开(公告)日：2004-10-19

申请号：US09978349

申请日：2001-10-15

申请人： Stephen C. Ennis ,  Larry D. Hewitt

发明人： Stephen C. Ennis ,  Larry D. Hewitt

IPC分类号： G06F1300

CPC分类号： G06F13/128

摘要： A computer system I/O node. An input/output node for a computer system includes a first receiver unit configured to receive a first command on a first communication path and a first transmitter unit coupled to transmit a first corresponding command that corresponds to the first command on a second communication path. The input/output node also includes a second receiver unit configured to receive a second command on a third communication path and a second transmitter unit coupled to transmit a second corresponding command that corresponds to the second command on a fourth communication path. Further, the input/output node includes a bridge unit coupled to receive selected commands from the first receiver and the second receiver and configured to transmit commands corresponding to the selected commands upon a peripheral bus.

摘要翻译： 计算机系统I / O节点。 用于计算机系统的输入/输出节点包括被配置为在第一通信路径上接收第一命令的第一接收器单元和耦合以在第二通信路径上发送对应于第一命令的第一对应命令的第一发送器单元。 输入/输出节点还包括被配置为在第三通信路径上接收第二命令的第二接收器单元和耦合以在第四通信路径上发送对应于第二命令的第二对应命令的第二发送器单元。 此外，输入/输出节点包括耦合以从第一接收器和第二接收器接收所选命令的桥单元，并且被配置为在外围总线上发送与所选命令相对应的命令。

公开(公告)号：US5918073A

公开(公告)日：1999-06-29

申请号：US884432

申请日：1997-06-27

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： G06F3/06 ,  G06F3/16 ,  G06F5/10 ,  G06F3/00

CPC分类号： G06F5/10 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0674 ,  G06F3/16

摘要： A system and method are presented for equalizing data buffer storage and fetch rates of peripheral devices. A computer system of the present invention includes a central processing unit (CPU), first and second peripheral devices, and a data buffer. The first peripheral device stores data within the data buffer, and the second peripheral device fetches data from the data buffer. A fraction of the data buffer contains unread data (i.e. data stored within the data buffer by the first peripheral device and not yet fetched by the second peripheral device). The first peripheral device includes a reload register, the contents of which determines the rate at which the first peripheral device stores data within the data buffer. The CPU produces a reload value, which is stored within the reload register, such that the rate at which the first peripheral device stores the data within the data buffer is made substantially equal to the rate at which the second peripheral device fetches the data from the data buffer. The data buffer is preferably operated a first-in-first-out manner, and includes a write pointer and a read pointer. The CPU preferably produces the reload value such that approximately half the memory locations within the data buffer contain unread data at any given time.

摘要翻译： 提出了一种系统和方法，用于平衡外围设备的数据缓冲存储和提取速率。 本发明的计算机系统包括中央处理单元（CPU），第一和第二外围设备以及数据缓冲器。 第一外围设备将数据存储在数据缓冲器内，第二外围设备从数据缓冲器中取出数据。 数据缓冲器的一小部分包含未读数据（即由第一外围设备存储在数据缓冲器内并且尚未被第二外围设备取出的数据）。 第一外围设备包括重新加载寄存器，其内容确定第一外围设备在数据缓冲器内存储数据的速率。 CPU产生存储在重新加载寄存器内的重载值，使得第一外围设备将数据存储在数据缓冲器内的速率基本上等于第二外围设备从数据缓冲器中提取数据的速率 数据缓冲区。 数据缓冲器优选地以先进先出的方式操作，并且包括写指针和读指针。 CPU优选地产生重载值，使得数据缓冲器内的大约一半存储器位置在任何给定时间包含未读数据。

公开(公告)号：US5898886A

公开(公告)日：1999-04-27

申请号：US752647

申请日：1996-11-19

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： G06F13/42

CPC分类号： G06F13/423

摘要： A computer system is presented having various peripheral devices coupled to a PCI local bus (i.e., an expansion bus), a subset of the peripheral devices having quaternary interfaces configured to communicate via quaternary signals conveyed upon the PCI local bus. The various peripheral devices may include a video/graphics card, a sound card, a hard disk drive, a CD-ROM drive, and a network interface card. When data is transferred from a master device to a target device, and the master and target devices both have quaternary interfaces, the master device converts the data to quaternary signals before transmitting the data the target device via the PCI local bus. The target device receives the quaternary signals from the PCI local bus and converts the quaternary signals to the binary data. Two binary digits (i.e., bits) of information are advantageously conveyed using quaternary signals in the time required to transmit a single bit using binary signals, thus providing increased efficiency and reduced bus bandwidth requirements. If either device does not include a quaternary interface, the data is transferred using conventional binary signals. A handshaking protocol may be used to determine if both the master and target devices include a quaternary interface. The handshaking protocol is implemented using handshaking signals conveyed over additional control lines added to the PCI local bus. Alternatively, a configuration memory may be included in the quaternary interface of the master device to reduce the required number of additional control lines from two to one.

摘要翻译： 呈现具有耦合到PCI本地总线（即，扩展总线）的各种外围设备的计算机系统，具有被配置为经由PCI本地总线上传送的四进制信号进行通信的四进制接口的外围设备的子集。 各种外围设备可以包括视频/图形卡，声卡，硬盘驱动器，CD-ROM驱动器和网络接口卡。 当数据从主设备传输到目标设备，并且主设备和目标设备都具有四元接口时，主设备在通过PCI本地总线传送目标设备的数据之前将数据转换为四进制信号。 目标设备从PCI本地总线接收四进制信号，并将四进制信号转换为二进制数据。 在使用二进制信号发送单个位所需的时间内，使用四进制信号有利地传送信息的两个二进制数字（即比特），从而提供更高的效率和降低的总线带宽要求。 如果任何一个设备不包括四元接口，则使用常规二进制信号传输数据。 握手协议可用于确定主设备和目标设备是否包括四元接口。 使用通过添加到PCI本地总线的附加控制线传送的握手信号实现握手协议。 或者，可以在主设备的四元接口中包括配置存储器，以将所需数量的附加控制线从两个减少到一个。

公开(公告)号：US5859995A

公开(公告)日：1999-01-12

申请号：US373689

申请日：1995-01-17

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： H03K19/003 ,  G06F3/16 ,  G06F7/02 ,  G06F9/38 ,  G10H1/00 ,  G10H1/12 ,  G10H7/00 ,  G10H7/02 ,  H03K3/02 ,  H03K23/68 ,  H03M3/02 ,  H03M7/32 ,  G06F1/04

CPC分类号： G06F3/16 ,  G06F7/026 ,  G06F9/3869 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  G10H7/02 ,  H03K23/68 ,  G10H2220/315 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/605 ,  G10H2250/611

摘要： A triggering circuit obviates propagation differences in differential combinatorial logic clocking of upstream and downstream state machines ("SM's"). The triggering circuit imposes an output state on the downstream SM in response to the appearance of an appropriate combination of the upstream SM output state and selected data at the triggering circuit input. The triggering circuit and the upstream SM are clocked from a common signal preventing the upstream SM from changing state before the triggering circuit produces the proper signal to impose the expected state on the downstream SM. The downstream SM takes on the correct output state in dependable correspondence with a selected upstream SM output state. In a preferred embodiment, a D flip-flop generates a triggering signal in response to a selected combination of upstream SM output state and system data. The D flip-flop triggering signal imposes a selected output state on a downstream SM through the asynchronous SET and CLEAR inputs of the downstream SM flip-flops. Because the D flip-flop and upstream SM are both clocked off the same trailing edge of the WRITE line, the upstream SM and D flip-flop change state together, preventing the upstream SM from changing state before the triggering signal is generated.

摘要翻译： 触发电路消除上游和下游状态机（“SM”）的差分组合逻辑时钟的传播差异。 触发电路响应于在触发电路输入处出现上游SM输出状态和所选择的数据的适当组合，在下游SM上施加输出状态。 触发电路和上游SM从公共信号计时，防止上游SM在触发电路产生适当信号之前改变状态，以将预期状态施加在下游SM上。 下游SM与选择的上游SM输出状态可靠地对应地进行正确的输出状态。 在优选实施例中，D触发器响应于所选择的上游SM输出状态和系统数据的组合而产生触发信号。 D触发器触发信号通过下游SM触发器的异步SET和CLEAR输入在下游SM上施加选择的输出状态。 因为D触发器和上游SM都被写入WRITE线的相同后沿，所以上行SM和D触发器一起改变状态，从而防止上游SM在产生触发信号之前改变状态。

公开(公告)号：US07607031B2

公开(公告)日：2009-10-20

申请号：US11482269

申请日：2006-07-07

申请人： Paul A. Mackey ,  Paul C. Miranda ,  Larry D. Hewitt ,  Jonathan M. Owen

发明人： Paul A. Mackey ,  Paul C. Miranda ,  Larry D. Hewitt ,  Jonathan M. Owen

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

摘要： A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters a training phase in which training patterns are transmitted over the communication link for a predetermined time period. The communication link returns to the power savings mode after the predetermined time period has elapsed. At least one sideband signal, separate from the communication link, and coupled between the first and second integrated circuits, is used to indicate when to enter the training phase from the power savings mode and exit the training phase and return to the power savings mode.

摘要翻译： 计算机系统包括通过通信链路耦合的第一和第二集成电路。 通信链路以省电模式运行，其中数据不通过链路发送。 周期性地，通信链路进入训练阶段，其中通过通信链路在预定时间段内传送训练模式。 在预定时间段过去之后，通信链路返回到省电模式。 与通信链路分离并且耦合在第一和第二集成电路之间的至少一个边带信号用于指示何时从功率节省模式进入训练阶段并退出训练阶段并返回到省电模式。

公开(公告)号：US06928528B1

公开(公告)日：2005-08-09

申请号：US10266118

申请日：2002-10-07

申请人： Larry D. Hewitt

发明人： Larry D. Hewitt

IPC分类号： G06F12/06 ,  G06F13/40 ,  H04L7/02 ,  H04L12/46

CPC分类号： H04L12/4625 ,  G06F13/4059 ,  H04L7/005 ,  H04L7/02

摘要： A method and apparatus for guaranteed data synchronization. In one embodiment, a data synchronization unit includes a memory unit, a write pointer unit, a read pointer unit, and synchronization pulse logic. The memory unit may receive information from a source external to the data synchronization unit. The write pointer may specify an address within the memory where incoming information is to be written. A read pointer outgoing information is to be read from. The data synchronization unit may also include synchronization pulse logic. The synchronization pulse logic may be configured to, in a synchronization mode, to generate a synchronization pulse. In response to an assertion of the synchronization pulse, the read pointer may be initialized such that data read out of the memory unit is valid (i.e. guaranteed to meet electrical requirements) at that time.

摘要翻译： 一种用于保证数据同步的方法和装置。 在一个实施例中，数据同步单元包括存储器单元，写指针单元，读指针单元和同步脉冲逻辑。 存储器单元可以从数据同步单元外部的源接收信息。 写指针可以指定存储器内的地址，其中输入信息将被写入。 读取指针传出信息将被读取。 数据同步单元还可以包括同步脉冲逻辑。 同步脉冲逻辑可以被配置为在同步模式下产生同步脉冲。 响应于同步脉冲的断言，可以对读指针进行初始化，使得从存储器单元读出的数据在此时有效（即保证满足电气要求）。