公开(公告)号：US07519780B2

公开(公告)日：2009-04-14

申请号：US11556346

申请日：2006-11-03

申请人： Jonathan J. DeMent ,  Roy M. Kim ,  Alvan W. Ng ,  Kevin C. Stelzer ,  Thuong Q. Truong

发明人： Jonathan J. DeMent ,  Roy M. Kim ,  Alvan W. Ng ,  Kevin C. Stelzer ,  Thuong Q. Truong

IPC分类号： G06F12/00

CPC分类号： G06F12/0817

摘要： A system and method for reducing store latency in symmetrical multiprocessor systems are provided. Bus agents are provided which monitor reflected ownership requests (Dclaims) to determine if the reflected Dclaim is its own Dclaim. If so, the bus agent determines that it is the winner of the ownership request and can immediately perform data modification using its associated local cache. If the bus agent determines that the reflected Dclaim does not match its own Dclaim, it determines that it is the loser of the ownership request and invalidates the corresponding cache line in its own local cache. The loser bus agent may then send a Read With Intent to Modify request to obtain the data from another cache and place it into its own cache for modification. These operations are performed without the need for a Kill request and without having to perform retries of a losing ownership request.

摘要翻译： 提供了一种用于在对称多处理器系统中减少存储延迟的系统和方法。 提供巴士代理，监控反映的所有权请求（Dclaims），以确定反映的Dclaim是否是自己的Dclaim。 如果是这样，总线代理确定它是所有权请求的获胜者，并且可以使用其关联的本地高速缓存立即执行数据修改。 如果总线代理确定反映的Dclaim与其自己的Dclaim不匹配，则它确定它是所有权请求的输家，并使其本地缓存中的相应缓存行无效。 失败者总线代理可以随后发送读取有意图修改请求以从另一个高速缓存获取数据并将其放入其自己的高速缓存中进行修改。 这些操作在不需要杀死请求的情况下执行，而不必执行失败的所有权请求的重试。

公开(公告)号：US20080109585A1

公开(公告)日：2008-05-08

申请号：US11556346

申请日：2006-11-03

申请人： Jonathan J. DeMent ,  Roy M. Kim ,  Alvan W. Ng ,  Kevin C. Stelzer ,  Thuong Q. Truong

发明人： Jonathan J. DeMent ,  Roy M. Kim ,  Alvan W. Ng ,  Kevin C. Stelzer ,  Thuong Q. Truong

IPC分类号： G06F13/364

CPC分类号： G06F12/0817

摘要： A system and method for reducing store latency in symmetrical multiprocessor systems are provided. Bus agents are provided which monitor reflected ownership requests (Dclaims) to determine if the reflected Dclaim is its own Dclaim. If so, the bus agent determines that it is the winner of the ownership request and can immediately perform data modification using its associated local cache. If the bus agent determines that the reflected Dclaim does not match its own Dclaim, it determines that it is the loser of the ownership request and invalidates the corresponding cache line in its own local cache. The loser bus agent may then send a Read With Intent to Modify request to obtain the data from another cache and place it into its own cache for modification. These operations are performed without the need for a Kill request and without having to perform retries of a losing ownership request.

摘要翻译： 提供了一种用于在对称多处理器系统中减少存储延迟的系统和方法。 提供巴士代理，监控反映的所有权请求（Dclaims），以确定反映的Dclaim是否是自己的Dclaim。 如果是这样，总线代理确定它是所有权请求的获胜者，并且可以使用其关联的本地高速缓存立即执行数据修改。 如果总线代理确定反映的Dclaim与其自己的Dclaim不匹配，则它确定它是所有权请求的输家，并使其本地缓存中的相应缓存行无效。 失败者总线代理可以随后发送读取有意图修改请求以从另一个高速缓存获取数据并将其放入其自己的高速缓存中进行修改。 这些操作在不需要杀死请求的情况下执行，而不必执行失败的所有权请求的重试。

公开(公告)号：US20080168318A1

公开(公告)日：2008-07-10

申请号：US11621766

申请日：2007-01-10

申请人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

发明人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

IPC分类号： G01R31/30 ,  G06F11/00

CPC分类号： G01R31/3004 ,  G01R31/31721 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.

摘要翻译： 提供了一种电压标识符（VID）分类系统，其以恒定的处理器频率优化处理器功率和工作电压保护带。 VID分选系统确定处理器的电压与电流曲线。 然后，VID分选系统使用电压与电流特性来计算每个VID的功率，以确定最大功率标准内的VID的可接受范围。 VID分类系统然后测试该范围内的VID，并从该范围中选择一个VID，以在恒定的处理器频率下对最小功率和/或最大电压保护带进行优化。

公开(公告)号：US20080034193A1

公开(公告)日：2008-02-07

申请号：US11462601

申请日：2006-08-04

申请人： Michael N. Day ,  Jonathan J. DeMent ,  Charles R. Johns ,  Orran Y. Krieger ,  Cathy May

发明人： Michael N. Day ,  Jonathan J. DeMent ,  Charles R. Johns ,  Orran Y. Krieger ,  Cathy May

IPC分类号： G06F7/38

CPC分类号： G06F13/24 ,  G06F9/32 ,  G06F9/4812 ,  G06F2209/481

摘要： A system and method for providing a mediated external exception extension for a microprocessor are provided. With the system and method, in response to an external exception, a hypervisor determines if the associated external interrupt is directed to a logical partition (LPAR) that has external interrupt handling enabled. If so, the hypervisor sets appropriate state restore registers (SRRs) and passes control to an external interrupt handler of the LPAR. If external interrupt handling is not currently enabled by the LPAR, the hypervisor sets a mediated exception request and returns control to the LPAR. Once the operating system of the logical partition re-enables external interrupt handling, a mediated external interrupt occurs, state information for the LPAR is set in the SRRs, and the external interrupt handler of the LPAR is invoked. In this way, external interrupts may be received by the hypervisor even when external interrupt handling is disabled.

摘要翻译： 提供了一种用于为微处理器提供介导的外部异常扩展的系统和方法。 利用系统和方法，响应于外部异常，管理程序确定相关联的外部中断是否被引导到启用了外部中断处理的逻辑分区（LPAR）。 如果是这样，管理程序设置适当的状态恢复寄存器（SRR），并将控制权传递给LPAR的外部中断处理程序。 如果LPAR当前未启用外部中断处理，管理程序将设置介入的异常请求并将控制权返回给LPAR。 一旦逻辑分区的操作系统重新启用外部中断处理，就会发生中介的外部中断，LPAR的状态信息设置在SRR中，并且调用LPAR的外部中断处理程序。 以这种方式，即使禁用外部中断处理，管理程序也可以接收外部中断。

公开(公告)号：US08230495B2

公开(公告)日：2012-07-24

申请号：US12413016

申请日：2009-03-27

申请人： Robert W. Berry, Jr. ,  Jonathan J. DeMent ,  John S. Liberty

发明人： Robert W. Berry, Jr. ,  Jonathan J. DeMent ,  John S. Liberty

IPC分类号： G06F21/00

CPC分类号： H04L9/32 ,  G06F21/75 ,  H04L2209/34 ,  H04L2209/56

摘要： A method for electronically fused encryption key security includes inserting a plurality of inverters between a bank of security fuses and a fuse sense logic module. The method also includes sensing an activated set of the bank of security fuses and the plurality of inverters. The method further includes comparing the sensed activated set of the bank of security fuses and the plurality of inverters with a software key to determine whether at least a substantial match is made.

摘要翻译： 一种用于电子融合加密密钥安全性的方法包括在安全保险丝组和熔丝检测逻辑模块之间插入多个逆变器。 该方法还包括感测安全熔断器组和多个逆变器的激活组。 该方法还包括将感测到的安全熔断器组和多个逆变器的激活组与软件密钥进行比较，以确定是否至少进行了实质的匹配。

公开(公告)号：US07917347B2

公开(公告)日：2011-03-29

申请号：US11927840

申请日：2007-10-30

申请人： Makoto Aikawa ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian K. Flachs ,  Gilles Gervais ,  Iwao Takiguchi ,  Tetsuji Tamura

发明人： Makoto Aikawa ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian K. Flachs ,  Gilles Gervais ,  Iwao Takiguchi ,  Tetsuji Tamura

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G01R31/318364

摘要： Mechanisms for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.

摘要翻译： 提供了用于产生用于集成电路器件测试的最坏情况电流波形的机构。 首先执行集成电路装置的结构分析，以确定要应用于集成电路装置的初始最坏情况功率工作负荷。 此后，将得到的最坏情况功率工作量应用于模型，并且被模拟以产生输入到集成电路器件的电气模型以产生最坏情况噪声预算值的最坏情况电流波形。 然后将最坏情况的噪声预算值与从最坏情况功率工作负载应用于硬件实现的集成电路设备的测量噪声进行比较。 可以选择最坏情况下的电流波形以用于集成电路设备的未来测试，或者可以对仿真模型进行修改，并且基于比较的结果重复该过程。

公开(公告)号：US07447602B1

公开(公告)日：2008-11-04

申请号：US11758034

申请日：2007-06-05

申请人： Douglas H. Bradley ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino

发明人： Douglas H. Bradley ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino

IPC分类号： G01R21/00 ,  G01R21/06

CPC分类号： G01R31/31721 ,  G01R31/31718

摘要： A system and method for sorting processor chips based on a thermal design point are provided. With the system and method, for each processor chip, a high power workload is run on the processor chip to determine a voltage regulator module (VRM) load line. Thereafter, a thermal design point (TDP) workload is applied to the processor chip and the voltage is varied until a performance of the processor chip falls on the VRM load line. At this point, the power input to the processor chip is measured and used to sort, or bin, the processor chip. The various workloads applied have a constant frequency. From this sorting of processor chips, high speed processors that require less voltage to achieve a desired frequency and low current processors that drain less current while running at a desired frequency may be identified.

摘要翻译： 提供了一种基于热设计点分类处理器芯片的系统和方法。 利用系统和方法，对于每个处理器芯片，在处理器芯片上运行高功率工作负载以确定电压调节器模块（VRM）负载线。 此后，将热设计点（TDP）工作量应用于处理器芯片，并且改变电压直到处理器芯片的性能落在VRM负载线上。 此时，对处理器芯片的电源输入进行测量并用于对处理器芯片进行排序或分页。 应用的各种工作负载具有恒定的频率。 从处理器芯片的这种排序中，可以识别需要较少电压以实现期望频率的低速处理器和在期望频率下运行时消耗较少电流的低电流处理器。