公开(公告)号：US07398342B2

公开(公告)日：2008-07-08

申请号：US11216353

申请日：2005-08-31

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G11C7/10

CPC分类号： G06F13/4086

摘要： A method and apparatus are provided for active termination control in a memory by a module register providing an active termination control signal to the memory. The memory turns on active termination based on information programmed into one or more mode registers of the memory. The memory maintains the active termination in an on state for a predetermined time based on information programmed into one or more mode registers of the memory.

摘要翻译： 提供了一种方法和装置，用于通过模块寄存器向存储器中的主动终止控制提供活动终止控制信号给存储器。 存储器根据编程到存储器的一个或多个模式寄存器中的信息，开启有效终止。 存储器基于编程到存储器的一个或多个模式寄存器中的信息，将活动终止维持在接通状态达预定时间。

公开(公告)号：US20080137439A1

公开(公告)日：2008-06-12

申请号：US12031347

申请日：2008-02-14

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G11C7/10 ,  H01L21/44

CPC分类号： G11C7/1078 ,  G11C5/02 ,  G11C5/04 ,  G11C7/109 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2254 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01055

摘要： Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.

摘要翻译： 本发明的实施例涉及用于存储器和存储器堆叠应用的可配置输入和/或输出。 更具体地，本发明的实施例包括存储器件，其包括具有配置为通过特定信号实现的电路的管芯，被配置为接收特定信号的输入引脚，以及路径选择器，其被配置为选择性地指定到电路的信号路径 从输入引脚。

公开(公告)号：US07145815B2

公开(公告)日：2006-12-05

申请号：US11215988

申请日：2005-08-31

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G11C7/00

CPC分类号： G06F13/4086

摘要： A method and apparatus are provided for active termination control in a memory by an module register providing an active termination control signal to the memory. The module register monitors a system command bus for read and write commands. In response to detecting a read or write command, the module register generates an active termination control signal to the memory. The memory turns on active termination based on information programmed into one or more mode registers of the memory. The memory maintains the active termination in an on state for a predetermined time based on information programmed into one or more mode registers of the memory.

摘要翻译： 提供了一种方法和装置，用于通过模块寄存器向存储器中的主动终止控制提供活动终止控制信号给存储器。 模块寄存器监视系统命令总线以进行读写命令。 响应于检测到读或写命令，模块寄存器产生到存储器的有效终止控制信号。 存储器根据编程到存储器的一个或多个模式寄存器中的信息，开启有效终止。 存储器基于编程到存储器的一个或多个模式寄存器中的信息，将活动终止维持在接通状态达预定时间。

公开(公告)号：US07126863B2

公开(公告)日：2006-10-24

申请号：US11216207

申请日：2005-08-31

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G11C7/00

CPC分类号： G06F13/4086

摘要： A method and apparatus are provided for active termination control in a memory. The memory turns on active termination based on information programmed into one or more mode registers of the memory. The memory maintains the active termination in an on state for a predetermined time based on information programmed into one or more mode registers of the memory.

摘要翻译： 提供了一种用于存储器中的主动终止控制的方法和装置。 存储器根据编程到存储器的一个或多个模式寄存器中的信息，开启有效终止。 存储器基于编程到存储器的一个或多个模式寄存器中的信息，将活动终止维持在接通状态达预定时间。

公开(公告)号：US07082491B2

公开(公告)日：2006-07-25

申请号：US11173862

申请日：2005-07-01

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G06F12/00

CPC分类号： G11C7/1018 ,  G11C7/1021 ,  G11C7/103 ,  G11C8/04

摘要： An apparatus enables the reordering of a block of n-bit words output from a plurality of memory cells according to information in certain address bits before outputting at least one n-bit word from a memory device while ignoring those certain address bits before inputting at least one n-bit word into the plurality of memory cells. The apparatus may additionally comprise examining at least two of the least significant bits of a column address and wherein the reordering is responsive to the examining. Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA0–CA2 identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA0–CA2 being “don't care” bits assumed to be 000.

摘要翻译： 一种装置能够在从存储装置输出至少一个n位字之前，根据某些地址位中的信息重新排序从多个存储单元输出的n位字，同时忽略那些某些地址位，至少输入 一个n位字到多个存储单元中。 所述装置还可以包括检查列地址的至少两个最低有效位，并且其中所述重新排序响应于所述检查。 因此，对于读取，由最高有效列地址位识别特定的8位突发，而最低有效位CA 0 -CA 2识别关键字之后的最关键字和读回卷序。 对于写入，突发由最重要的列地址识别，CA 0 -CA 2被认为是“不在乎”位。

公开(公告)号：US09466344B2

公开(公告)日：2016-10-11

申请号：US13489246

申请日：2012-06-05

申请人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

发明人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

IPC分类号： G06F12/10 ,  G11C7/10 ,  G11C11/4076

CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

公开(公告)号：US08438329B2

公开(公告)日：2013-05-07

申请号：US12986947

申请日：2011-01-07

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1684 ,  G11C5/025 ,  G11C5/04

摘要： An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.

公开(公告)号：US08253230B2

公开(公告)日：2012-08-28

申请号：US12121654

申请日：2008-05-15

申请人： Jeffery W. Janzen ,  Russell D. Slifer, legal representative ,  Michael Chaine ,  Kyle K. Kirby ,  William M. Hiatt

发明人： Jeffery W. Janzen ,  Michael Chaine ,  Kyle K. Kirby ,  William M. Hiatt

IPC分类号： H01L21/70 ,  H01L23/02 ,  H01L23/52

CPC分类号： H01L23/481 ,  H01L21/50 ,  H01L21/76898 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H01L23/60 ,  H01L23/62 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0248 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/13034 ,  H01L2924/00014

摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.

摘要翻译： 本文公开了直通3D互连和微电子管芯以及包括这种互连以禁用电连接的堆叠管芯的系统。 在一个实施例中，堆叠管芯的系统包括具有背面的第一微电子管芯，经由第一管芯延伸到背面的互连件，电耦合到互连的集成电路，以及与第一静电放电（ESD）器件电隔离的第一静电放电 互连。 第二微电子管芯具有耦合到第一管芯的背侧的前侧，电连接到互连的前侧的金属接触件和电耦合到金属接触件的第二ESD器件。 在另一实施例中，第一管芯还包括承载集成电路和第一ESD器件的衬底，并且互连件位于衬底中，以禁止第一ESD器件和互连件之间的电连接。

公开(公告)号：US20090283898A1

公开(公告)日：2009-11-19

申请号：US12121654

申请日：2008-05-15

申请人： Jeffery W. Janzen ,  Michael Chaine ,  Kyle K. Kirby ,  William M. Hiatt ,  Russell D. Slifer

发明人： Jeffery W. Janzen ,  Michael Chaine ,  Kyle K. Kirby ,  William M. Hiatt ,  Russell D. Slifer

IPC分类号： H01L23/52 ,  H01L23/538 ,  H01L21/50 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/50 ,  H01L21/76898 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H01L23/60 ,  H01L23/62 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0248 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/13034 ,  H01L2924/00014

摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.

摘要翻译： 本文公开了直通3D互连和微电子管芯以及包括这种互连以禁用电连接的堆叠管芯的系统。 在一个实施例中，堆叠管芯的系统包括具有背面的第一微电子管芯，经由第一管芯延伸到背面的互连件，电耦合到互连的集成电路，以及与第一静电放电（ESD）器件电隔离的第一静电放电 互连。 第二微电子管芯具有耦合到第一管芯的背侧的前侧，电连接到互连的前侧的金属接触件和电耦合到金属接触件的第二ESD器件。 在另一实施例中，第一管芯还包括承载集成电路和第一ESD器件的衬底，并且互连件位于衬底中，以禁止第一ESD器件和互连件之间的电连接。

公开(公告)号：US07519877B2

公开(公告)日：2009-04-14

申请号：US10915663

申请日：2004-08-10

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G11C29/46 ,  G11C29/54

CPC分类号： G11C29/46

摘要： Apparatus and methods of forming and operating the apparatus provide an instrumentality for a memory to generate a test mode signal to trigger a test in response to the memory detecting a predetermined command from a system bus. In an embodiment, a mode register in the memory includes an indicator to enable or disable issuance of a test mode signal from the memory. The mode register may contain information identifying the predetermined command.

摘要翻译： 形成和操作该设备的装置和方法为存储器提供了一种工具，用于产生测试模式信号，以响应于存储器检测来自系统总线的预定命令来触发测试。 在一个实施例中，存储器中的模式寄存器包括用于使能或禁止从存储器发出测试模式信号的指示器。 模式寄存器可以包含标识预定命令的信息。