公开(公告)号：US09064072B2

公开(公告)日：2015-06-23

申请号：US13562393

申请日：2012-07-31

申请人： Jeffrey S. Brown

发明人： Jeffrey S. Brown

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/50 ,  G06F17/5068 ,  G06F17/5081

摘要： Disclosed are embodiments for modeling semiconductor device performance using a single compact model despite changes in performance attribute to model parameter dependency of a single semiconductor device that occur during fitting and/or re-centering due to local layout effects (LLEs) and despite variations in this dependency across multiple related semiconductor devices due to LLEs. In one embodiment, the actual performance attribute to model parameter dependence of a single semiconductor device is fit to a reference dependence so that changes to the compact model are not required even when changes occur in the performance attribute to model parameter dependency during fitting and/or re-centering. In another embodiment, the actual performance attribute to model parameter dependence of each of multiple related semiconductor devices are fit to a reference dependence so that changes to the compact model are not required even when the performance attribute to model parameter dependency varies across the devices.

摘要翻译： 公开了使用单个紧凑型模型来建模半导体器件性能的实施例，尽管由于局部布局效应（LLE）而在拟合和/或重新对中期间发生的单个半导体器件的性能属性与模型参数依赖性的变化，并且尽管在该 由于LLE引起的多个相关半导体器件的依赖性。 在一个实施例中，单个半导体器件的模型参数依赖性的实际性能属性适合于参考依赖性，使得即使在性能属性中发生改变以在拟合和/或模拟参数依赖性期间发生变化，也不需要对紧凑模型的改变 重新定心 在另一个实施例中，对于多个相关半导体器件中的每一个的模型参数依赖性的实际性能属性适合于参考依赖性，使得即使当器件的性能属性与模型参数依赖性变化时，也不需要对紧凑模型的改变。

公开(公告)号：US20120105123A1

公开(公告)日：2012-05-03

申请号：US12938172

申请日：2010-11-02

申请人： Jeffrey S. Brown ,  Mark Franklin Turner

发明人： Jeffrey S. Brown ,  Mark Franklin Turner

IPC分类号： H03H11/26

CPC分类号： G06F1/10 ,  H03K5/133 ,  H03K2005/00215

摘要： An apparatus for controlling clock skew in an integrated circuit (IC) includes timing circuitry operative to generate a clock signal for distribution in the IC and at least one buffer circuit operative to receive the clock signal, or a signal indicative of the clock signal, and to generate a delayed version of the clock signal as an output thereof. The buffer circuit includes at least first and second inverter stages and a resistive-capacitive (RC) loading structure. An output of the first inverter stage is connected to an input of the second inverter stage via the RC loading structure. The buffer circuit has a delay associated therewith that is selectively varied as a function of one or more adjustable characteristics of the RC loading structure. Clock skew in the IC is controlled as a function of the delay of the buffer circuit.

摘要翻译： 一种用于控制集成电路（IC）中的时钟偏差的装置，包括：时钟电路，用于产生用于在IC中分配的时钟信号，以及至少一个可操作以接收时钟信号的缓冲电路或指示时钟信号的信号;以及 以产生时钟信号的延迟版本作为其输出。 缓冲电路至少包括第一和第二反相器级和电阻电容（RC）加载结构。 第一逆变器级的输出经由RC加载结构连接到第二变换级的输入端。 缓冲电路具有与之相关的延迟，其随着RC加载结构的一个或多个可调整特性而有选择地变化。 作为缓冲电路的延迟的函数控制IC中的时钟偏移。

公开(公告)号：US20090164956A1

公开(公告)日：2009-06-25

申请号：US11962165

申请日：2007-12-21

申请人： Jonathan W. Byrn ,  Mark F. Turner ,  Jeffrey S. Brown

发明人： Jonathan W. Byrn ,  Mark F. Turner ,  Jeffrey S. Brown

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A method to redistribute current demand is presented. The method includes a first step of determining timing arc data for one or more timing arcs of a circuit design. The method includes a second step of checking the timing arc data for delay shift target cells. The method includes a further step of swapping a delay shift target cell with a delay shift cell.

摘要翻译： 介绍了一种重新分配当前需求的方法。 该方法包括确定电路设计的一个或多个定时弧的定时弧数据的第一步骤。 该方法包括检查用于延迟移位目标小区的定时弧数据的第二步骤。 该方法还包括用延迟移位单元交换延迟移位目标小区的另一步骤。

公开(公告)号：US20090134463A1

公开(公告)日：2009-05-28

申请号：US12348344

申请日：2009-01-05

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, JR. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, JR. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

IPC分类号： H01L29/78

CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.

摘要翻译： 一种半导体结构和用于制造集成电路芯片的系统。 半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。 用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。

公开(公告)号：US07466171B2

公开(公告)日：2008-12-16

申请号：US11623119

申请日：2007-01-15

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

IPC分类号： H03L7/00

CPC分类号： H03K5/153

摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.

摘要翻译： 一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。 隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。 第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。 随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。 运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

公开(公告)号：US20080250257A1

公开(公告)日：2008-10-09

申请号：US12038974

申请日：2008-02-28

申请人： Jeffrey S. Brown

发明人： Jeffrey S. Brown

IPC分类号： G06F1/26

CPC分类号： G06F1/3243 ,  G06F1/3225 ,  G06F1/3275 ,  G11C7/1006 ,  G11C7/22 ,  G11C16/10 ,  G11C16/26 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152

摘要： A method for conserving power in a device. The method generally includes the steps of (A) generating a polarity signal by analyzing a current one of a plurality of data items having a plurality of data bits, the polarity signal having an inversion bit indicating that the current data item is to be stored in one of (i) an inverted condition and (ii) a non-inverted condition relative to a normal condition such that a majority of the data bits have a first logic state, wherein reading one of the data bits having the first logic state consumes less power than reading one of the data bits having a second logic state, (B) selectively either (i) inverting the current data item or (ii) not inverting current the data item based on the inversion bit and (C) storing the current data item in a plurality of single-ended bit cells in the device.

摘要翻译： 一种节省设备功率的方法。 该方法通常包括以下步骤：（A）通过分析具有多个数据位的多个数据项中的当前一个数据项来产生极性信号，所述极性信号具有指示当前数据项将要存储的反转位 （i）反转条件和（ii）相对于正常条件的非反相条件之一，使得大多数数据位具有第一逻辑状态，其中读取具有第一逻辑状态的数据位中的一个消耗较少 （B）选择性地（i）反转当前数据项或（ii）基于反转位不反转当前数据项，（C）存储当前数据 项目在设备中的多个单端比特单元中。

公开(公告)号：US20080244474A1

公开(公告)日：2008-10-02

申请号：US11732092

申请日：2007-04-02

申请人： Mark F. Turner ,  Jonathan W. Byrn ,  Jeffrey S. Brown

发明人： Mark F. Turner ,  Jonathan W. Byrn ,  Jeffrey S. Brown

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method of managing a cell library regarding power optimization is disclosed. The method generally includes the steps of (A) reading a plurality of first modules within a first region of a circuit design stored in a design file, (B) calculating a first merit value indicating a relative sensitivity of the first region to a power consumption, the first merit value having a range from a static power dominated value to a dynamic power dominated value and (C) creating a constraint file configured to limit a design tool to a first subset of a plurality of replacement modules based on the first merit value such that the design tool automatically optimizes the power consumption of the first region by replacing at least one of the first modules with at least one of the replacement modules within the first subset, the replacement modules residing in a library file.

摘要翻译： 公开了一种管理关于功率优化的单元库的方法。 该方法通常包括以下步骤：（A）读取存储在设计文件中的电路设计的第一区域内的多个第一模块，（B）计算指示第一区域相对于功耗的相对灵敏度的第一优值值 所述第一优点值具有从静态功率主导值到动态功率主导值的范围，以及（C）创建约束文件，其被配置为基于所述第一优点值将设计工具限制到多个替换模块的第一子集 使得设计工具通过用第一子集内的至少一个替换模块替​​换至少一个第一模块来自动优化第一区域的功耗，所述替换模块驻留在库文件中。

公开(公告)号：US20080169844A1

公开(公告)日：2008-07-17

申请号：US11623119

申请日：2007-01-15

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

IPC分类号： H03K5/153

CPC分类号： H03K5/153

摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.

摘要翻译： 一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。 隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。 第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。 随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。 运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

公开(公告)号：US07163851B2

公开(公告)日：2007-01-16

申请号：US10227995

申请日：2002-08-26

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

IPC分类号： H01L21/84

CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

摘要： The present invention provides methods for fabrication of fin-type field effect transistors (FinFETs) and thick-body devices on the same chip using common masks and steps to achieve greater efficiency than prior methods. The reduction in the number of masks and steps is achieved by using common masks and steps with several scaling strategies. In one embodiment, the structure normally associated with a FinFET is created on the side of a thick silicon mesa, the bulk of which is doped to connect with a body contact on the opposite side of the mesa. The invention also includes FinFETs, thick-body devices, and chips fabricated by the methods.

摘要翻译： 本发明提供了使用公共掩模和步骤在相同芯片上制造鳍式场效应晶体管（FinFET）和厚体器件的方法，以实现比现有方法更高的效率。 通过使用具有多种缩放策略的常用掩模和步骤来实现掩模和步骤数量的减少。 在一个实施例中，通常与FinFET相关联的结构产生在厚硅台面的一侧，该厚硅台面的大部分被掺杂以与台面的相对侧上的身体接触连接。 本发明还包括FinFET，厚体器件和通过这些方法制造的芯片。

公开(公告)号：US07131103B2

公开(公告)日：2006-10-31

申请号：US10793055

申请日：2004-03-04

申请人： Jeffrey S. Brown

发明人： Jeffrey S. Brown

IPC分类号： G06F17/50

CPC分类号： G03F1/00 ,  H01L27/0207

摘要： A method for integrating a first integrated circuit design having first layers and a second integrated circuit design having second layers into a common reticle set. The second integrated circuit design has a given number of second layers and the first integrated circuit design has less than the given number of layers. At least one of the first layers is duplicated to produce at least one duplicated first layer until the first integrated circuit design has the given number of layers. The first layers and the at least one duplicated first layer are mapped to a modified first integrated circuit design having the given number of first layers. A reticle set is fabricated to include the given number of first layers and second layers, using the modified first integrated circuit design and the second integrated circuit design.

摘要翻译： 一种用于将具有第一层的第一集成电路设计和具有第二层的第二集成电路设计集成到公共掩模版集合中的方法。 第二集成电路设计具有给定数量的第二层，并且第一集成电路设计具有小于给定数量的层。 第一层中的至少一个被复制以产生至少一个复制的第一层，直到第一集成电路设计具有给定数量的层。 第一层和至少一个复制的第一层被映射到具有给定数量的第一层的修改的第一集成电路设计。 使用修改的第一集成电路设计和第二集成电路设计，制作掩模版组以包括给定数量的第一层和第二层。