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    Concurrent fin-fet and thick body device fabrication
    1.
    发明授权
    Concurrent fin-fet and thick body device fabrication 有权
    并发鳍和厚体器件制造

    公开(公告)号：US07473970B2

    公开(公告)日：2009-01-06

    申请号：US11481120

    申请日：2006-07-05

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

    摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

    摘要翻译： 集成电路芯片和半导体结构。 集成电路芯片包括：包含半导体台面和掺杂体接触的厚体器件; 以及在半导体台面的第一侧壁上的场效应晶体管，其中所述掺杂体接触在所述半导体台面的第二侧壁上，并且其中所述半导体台面设置在所述场效应晶体管和所述掺杂体接触之间。 半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。

    SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP
    2.
    发明申请
    SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP 有权
    用于制造集成电路芯片的半导体结构和系统

    公开(公告)号：US20090134463A1

    公开(公告)日：2009-05-28

    申请号：US12348344

    申请日：2009-01-05

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, JR. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, JR. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L29/78

    CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

    摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.

    摘要翻译： 一种半导体结构和用于制造集成电路芯片的系统。 半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。 用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。

    Semiconductor structure and system for fabricating an integrated circuit chip
    4.
    发明授权
    Semiconductor structure and system for fabricating an integrated circuit chip 有权
    用于制造集成电路芯片的半导体结构和系统

    公开(公告)号：US07872310B2

    公开(公告)日：2011-01-18

    申请号：US12348344

    申请日：2009-01-05

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L29/772

    CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

    摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.

    摘要翻译： 一种半导体结构和用于制造集成电路芯片的系统。 半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。 用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。

    Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
    6.
    发明授权
    Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure 失效
    基于相同测试结构的半导体应力诱发缺陷和反熔丝的测试结构和方法

    公开(公告)号：US06624031B2

    公开(公告)日：2003-09-23

    申请号：US09989850

    申请日：2001-11-20

    申请人： Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

    IPC分类号： H01L21336

    CPC分类号： H01L22/34 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may,be substituted for the diode. The use of the diode as an antifuse is also disclosed.

    摘要翻译： 一种检测半导体工艺应力诱发缺陷的方法。 该方法包括：提供多晶硅界限的测试二极管，二极管包括在硅衬底的第二区域的上部内的扩散的第一区域，与第一区域相反的掺杂剂类型的第二区域，第一区域由 外围电介质隔离，外围多晶硅栅极，包括介电层上的多晶硅层，栅极与第一区域的周边部分重叠; 强调二极管; 并且在应力期间监视施加二极管的栅极电流尖峰，确定正向偏置电压的斜率与预先选择的正向偏置电压下的第一区域电流的频率分布，并且在应力之后监视用于软击穿的二极管 。 二极管可代替DRAM单元。 还公开了使用二极管作为反熔丝。

    Method and structure to process thick and thin fins and variable fin to fin spacing
    8.
    发明授权
    Method and structure to process thick and thin fins and variable fin to fin spacing 有权
    处理厚薄翅片和可变翅片翅片间距的方法和结构

    公开(公告)号：US07301210B2

    公开(公告)日：2007-11-27

    申请号：US11306827

    申请日：2006-01-12

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211

    摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

    摘要翻译： 公开了一种集成电路，其具有在相同基板上具有不同宽度和可变间隔的多个半导体散热片。 形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。 翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。 翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。 具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。 可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET，或者替代地，各种单鳍和/或多鳍FET。

    High voltage N-LDMOS transistors having shallow trench isolation region
    9.
    发明授权
    High voltage N-LDMOS transistors having shallow trench isolation region 失效
    具有浅沟槽隔离区的高压N-LDMOS晶体管

    公开(公告)号：US06876035B2

    公开(公告)日：2005-04-05

    申请号：US10249766

    申请日：2003-05-06

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L23/58

    CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/7816

    摘要： A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.

    摘要翻译： 公开了一种用于晶体管的方法和结构，该晶体管具有栅极，栅极下方的沟道区，沟道区一侧的源极区，与源极区沟道区相反侧的漏极区，浅沟槽 在漏极区和沟道区之间的衬底中的隔离（STI）区，以及在STI区之下的漏极延伸。 漏极延伸沿着STI区域的底部并沿着STI的边的一部分定位。 沿着STI底部的漏极延伸部分可以包括不同于沿着STI侧面的漏极延伸部分的掺杂剂注入。 沿着STI侧面的排水延伸部分从STI的底部延伸到部分沿着STI侧面的位置。 STI区域位于栅极的一部分之下。 漏极延伸部在漏极区域和围绕STI的下周边的沟道区域之间提供导电路径。 漏极区域比源极区域更靠近栅极定位。