公开(公告)号：US20070152263A1

公开(公告)日：2007-07-05

申请号：US11687573

申请日：2007-03-16

Applicant: Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L29/788

CPC classification number: H01L27/1087 ,  H01L27/10832 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66181

Abstract: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

Abstract translation: 用于布置深沟槽和有源区域的动态随机存取存储器（DRAM）单元布局及其制造方法。 有源区域包括两个垂直晶体管，一个常见的位线触点和两个深沟槽。 第一垂直晶体管形成在第一深沟槽与第一栅极导电线部分重叠的区域上。 第二垂直晶体管形成在第二深沟槽与第二栅极导电线部分重叠的区域上。

公开(公告)号：US07109094B2

公开(公告)日：2006-09-19

申请号：US10972506

申请日：2004-10-25

Applicant: Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

Abstract translation: 浅沟槽隔离及其STI结构中防止潜行的方法。 提供具有形成在其上的焊盘层和沟槽的半导体衬底，随后在沟槽的侧壁上形成掺杂的第一衬里层。 然后在掺杂的第一衬里层上形成第二衬里层。 然后进行蚀刻以去除第一衬里层和第二衬里层的部分，使得第一衬里层的高度低于第二衬里层。 然后在焊盘层上形成牺牲层并填充沟槽。 然后进行扩散，使得第一衬里层中的掺杂离子扩散到衬底并在沟槽的两个底角之外形成漫射区。

公开(公告)号：US06958521B2

公开(公告)日：2005-10-25

申请号：US10639419

申请日：2003-08-11

Applicant: Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/762 ,  H01L29/00

CPC classification number: H01L21/76224

Abstract: Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

Abstract translation: 浅沟槽隔离及其STI结构中防止潜行的方法。 提供具有形成在其上的焊盘层和沟槽的半导体衬底，随后在沟槽的侧壁上形成掺杂的第一衬里层。 然后在掺杂的第一衬里层上形成第二衬里层。 然后进行蚀刻以去除第一衬里层和第二衬里层的部分，使得第一衬里层的高度低于第二衬里层。 然后在焊盘层上形成牺牲层并填充沟槽。 然后进行扩散，使得第一衬里层中的掺杂离子扩散到衬底并在沟槽的两个底角之外形成漫射区。

公开(公告)号：US06909136B2

公开(公告)日：2005-06-21

申请号：US10604344

申请日：2003-07-14

Applicant: Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

Inventor： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

IPC: H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

Abstract: A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

Abstract translation: 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

公开(公告)号：US20050127469A1

公开(公告)日：2005-06-16

申请号：US10972506

申请日：2004-10-25

Applicant: Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/762 ,  H01L21/20 ,  H01L21/76 ,  H01L29/00

CPC classification number: H01L21/76224

Abstract: Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

Abstract translation: 浅沟槽隔离及其STI结构中防止潜行的方法。 提供具有形成在其上的焊盘层和沟槽的半导体衬底，随后在沟槽的侧壁上形成掺杂的第一衬里层。 然后在掺杂的第一衬里层上形成第二衬里层。 然后进行蚀刻以去除第一衬里层和第二衬里层的部分，使得第一衬里层的高度低于第二衬里层。 然后在焊盘层上形成牺牲层并填充沟槽。 然后进行扩散，使得第一衬里层中的掺杂离子扩散到衬底并在沟槽的两个底角之外形成漫射区。

公开(公告)号：US20050012131A1

公开(公告)日：2005-01-20

申请号：US10604344

申请日：2003-07-14

Applicant: Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

Inventor： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

IPC: H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

Abstract: A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

Abstract translation: 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

公开(公告)号：US20090114968A1

公开(公告)日：2009-05-07

申请号：US12167231

申请日：2008-07-02

Applicant: Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

Inventor： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

IPC: H01L21/265 ,  H01L29/78 ,  H01L27/108

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

Abstract translation: 凹入栅极晶体管器件包括嵌入在半导体衬底中形成的栅极沟槽中的栅电极，其中栅极沟槽包括垂直侧壁和U形底部。 源区域设置在半导体衬底内的栅极沟槽的一侧。 漏极区域设置在其另一侧。 在栅电极和半导体衬底之间形成非对称栅介质层。 不对称栅极介电层在栅电极和漏极区之间具有第一厚度，并且在栅极和源极区之间具有第二厚度，其中第一厚度比第二厚度厚。

公开(公告)号：US07144799B2

公开(公告)日：2006-12-05

申请号：US11101007

申请日：2005-04-06

Applicant: Yinan Chen ,  Jeng-Ping Lin ,  Feng-Chuan Lin

Inventor： Yinan Chen ,  Jeng-Ping Lin ,  Feng-Chuan Lin

IPC: H01L21/44

CPC classification number: H01L21/76897 ,  H01L21/76895 ,  H01L27/10888

Abstract: Disclosed is a method for pre-retaining CB opening in a DRAM manufacture process, wherein a CB opening is filed with a photo-resist layer and an LPD oxidation layer that is filled at room temperature to avoid damaging caused by conventional etching techniques. The LPD oxidation layer and the photo-resist are replaced easily by a polysilicon layer and a BPSG layer.

Abstract translation: 公开了一种用于在DRAM制造工艺中预保留CB开口的方法，其中CB开口与在室温下填充的光致抗蚀剂层和LPD氧化层一起提供以避免由常规蚀刻技术引起的损坏。 LPD氧化层和光致抗蚀剂容易被多晶硅层和BPSG层所替代。

公开(公告)号：US20050082590A1

公开(公告)日：2005-04-21

申请号：US10972505

申请日：2004-10-25

Applicant: Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10832 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66181

Abstract: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

公开(公告)号：US06801462B2

公开(公告)日：2004-10-05

申请号：US10612857

申请日：2003-07-03

Applicant: Ming Cheng Chang ,  Jeng-Ping Lin ,  Tie Jiang Wu

Inventor： Ming Cheng Chang ,  Jeng-Ping Lin ,  Tie Jiang Wu

IPC: G11C700

CPC classification number: H01L27/10894 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  H01L22/34 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10891 ,  H01L27/10897

Abstract: A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices. In the test device, parallel first and second bar-type deep trenches capacitors are disposed in the scribe line region. The first and second bar-type deep trenches capacitors extend to the first and second pairs of memory cells in the memory region adjacent to the first active area respectively. The first and second bar-type deep trenches capacitors are electrically coupled to bit line contacts of the first and second pairs of memory cells respectively. First and second transistors have sources coupled to the first and second bar-type deep trenches capacitors respectively. A first bit line contact is electrically coupled to drains of the first and second transistors.

Abstract translation: 用于检测DRAM器件中的字线和深沟槽电容器的对准的测试装置和方法。 在测试装置中，平行的第一和第二条形深沟槽电容器设置在划线区域中。 第一和第二条形深沟槽电容器分别延伸到与第一有效区域相邻的存储器区域中的第一和第二对存储单元。 第一和第二条形深沟槽电容器分别电耦合到第一和第二对存储器单元的位线触点。 第一和第二晶体管分别具有耦合到第一和第二条形深沟槽电容器的源极。 第一位线接触件电耦合到第一和第二晶体管的漏极。