公开(公告)号：US20120185228A1

公开(公告)日：2012-07-19

申请号：US13426840

申请日：2012-03-22

申请人： Charles R. Johns

发明人： Charles R. Johns

IPC分类号： G06F17/50

CPC分类号： G06F12/0806 ,  G06F9/52 ,  G06F2209/521

摘要： A design structure for performing cacheline polling utilizing a store and reserve instruction are disclosed. In accordance with one embodiment of the present invention, a first process initially requests an action to be performed by a second process. A reservation is set at a cacheable memory location via a store operation. The first process reads the cacheable memory location via a load operation to determine whether or not the requested action has been completed by the second process. The load operation of the first process is stalled until the reservation on the cacheable memory location is lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.

摘要翻译： 公开了一种使用存储和预约指令执行高速缓存行轮询的设计结构。 根据本发明的一个实施例，第一过程最初请求通过第二过程执行动作。 通过存储操作在可高速缓存的存储器位置设置预留。 第一进程通过加载操作读取可高速缓存的存储器位置，以确定所请求的动作是否已由第二进程完成。 第一个进程的加载操作停止，直到可缓存的内存位置的预留丢失。 在请求的动作完成之后，可缓存存储器位置中的预留由第二进程复位。

公开(公告)号：US20120110348A1

公开(公告)日：2012-05-03

申请号：US12917092

申请日：2010-11-01

申请人： H. Peter Hofstee ,  Brian Flachs ,  Charles R. Johns

发明人： H. Peter Hofstee ,  Brian Flachs ,  Charles R. Johns

IPC分类号： G06F12/10 ,  G06F12/14

CPC分类号： G06F12/1009 ,  G06F12/1408

摘要： A system comprises a memory module configured to store signed page table data and a selected processing element coupled to the memory module. The selected processing element is one of a plurality of processing elements, which together comprise a portion of a multiprocessor system. The selected processing element is configured to authenticate page table management code and, based on authenticated page table management code, to sign page table data that is subsequently stored in the memory module, and to verify signed page table data that is read from the memory module.

摘要翻译： 系统包括被配置为存储经签名的页表数据的存储器模块和耦合到存储器模块的所选择的处理元件。 所选择的处理元件是多个处理元件之一，它们一起构成多处理器系统的一部分。 所选择的处理元件被配置为认证页表管理代码，并且基于经认证的页表管理代码来签名随后存储在存储器模块中的页表数据，并且验证从存储器模块读取的经签名页表数据 。

公开(公告)号：US08117389B2

公开(公告)日：2012-02-14

申请号：US12132460

申请日：2008-06-03

申请人： Charles R. Johns

发明人： Charles R. Johns

IPC分类号： G06F12/06

CPC分类号： G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/526 ,  G06F12/0815

摘要： A design structure for performing cacheline polling utilizing store and reserve and load when reservation lost instructions is disclosed. In one embodiment a method is provided which comprises storing a buffer flag busy indicator data value within a first cacheable memory location and setting a load/store operation reservation on said first cacheable memory location via a store and reserve instruction. In the described embodiment, a data value stored within the first cacheable memory location is accessed via a conditional load instruction in response to a determination that the load/store operation reservation on the first cacheable memory location has been reset. Conversely, execution of the conditional load instruction is stalled in response to a determination that the load/store operation reservation on the first cacheable memory location has not been reset.

摘要翻译： 一种用于当预约丢失指令被公开时利用存储和预留和加载来执行高速缓存线轮询的设计结构。 在一个实施例中，提供了一种方法，其包括将缓冲器标志忙指示符数据值存储在第一可缓存存储器位置内，并且经由存储和保留指令在所述第一可缓存存储器位置上设置加载/存储操作预留。 在所描述的实施例中，响应于第一可缓存存储器位置上的加载/存储操作预留被重置的确定，通过条件加载指令来存储存储在第一可缓存存储器位置内的数据值。 相反，响应于对第一可缓存存储器位置的加载/存储操作预留未被重置的确定，条件加载指令的执行被停止。

公开(公告)号：US08108905B2

公开(公告)日：2012-01-31

申请号：US11553008

申请日：2006-10-26

申请人： Charles R. Johns ,  Kanna Shimizu

发明人： Charles R. Johns ,  Kanna Shimizu

IPC分类号： H04L9/00 ,  H04N7/16 ,  G06F12/14 ,  G06F1/00 ,  G09C1/00 ,  G06F11/30

CPC分类号： G06F12/145 ,  G06F21/53

摘要： A system, method, and computer-usable medium for an isolated process to control address translation. According to a preferred embodiment of the present invention, an isolation region that is accessible only to a first processing unit in a data processing system is created. A loader is executed to load a secure process in the isolation region. If the secure process is determined to be allowed to issue real mode direct memory access commands, real mode direct memory access commands are enabled to allow the secure process to issue non-translated direct memory access commands.

摘要翻译： 用于控制地址转换的隔离过程的系统，方法和计算机可用介质。 根据本发明的优选实施例，创建了仅在数据处理系统中的第一处理单元可访问的隔离区域。 执行加载器以在隔离区域中加载安全处理。 如果确定安全过程被允许发出实模式直接存储器访问命令，则启用实模式直接存储器访问命令以允许安全过程发出非转换的直接存储器访问命令。

公开(公告)号：US08024489B2

公开(公告)日：2011-09-20

申请号：US12106483

申请日：2008-04-21

申请人： Michael N. Day ,  Charles R. Johns ,  Peichun P. Liu ,  Todd E. Swanson ,  Thuong Q. Truong

发明人： Michael N. Day ,  Charles R. Johns ,  Peichun P. Liu ,  Todd E. Swanson ,  Thuong Q. Truong

IPC分类号： G06F3/00

CPC分类号： G06F13/32 ,  G06F13/1642

摘要： A system for communicating command parameters between a processor and a memory flow controller is provided. The system makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

摘要翻译： 提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统。 该系统利用通道接口作为在处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。

公开(公告)号：US20110161643A1

公开(公告)日：2011-06-30

申请号：US12649860

申请日：2009-12-30

申请人： Alexandre E. Eichenberger ,  Brian K. Flachs ,  Charles R. Johns ,  Mark R. Nutter

发明人： Alexandre E. Eichenberger ,  Brian K. Flachs ,  Charles R. Johns ,  Mark R. Nutter

IPC分类号： G06F9/32

CPC分类号： G06F9/3887 ,  G06F8/4441 ,  G06F9/381 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3859

摘要： Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The mechanisms further execute the first parallel execution group and determining, for each iteration in the subset of iterations, whether the iteration has a data dependence. Moreover, the mechanisms commit store data to system memory only for stores performed by iterations in the subset of iterations for which no data dependence is determined. Store data of stores performed by iterations in the subset of iterations for which a data dependence is determined is not committed to the system memory.

摘要翻译： 提供了在运行时提取数据依赖关系的机制。 所述机制执行具有循环的一部分代码，并为所述循环生成包括小于所述循环的总迭代次数的循环迭代子集的第一并行执行组。 机制进一步执行第一个并行执行组，并确定迭代子集中的每个迭代，迭代是否具有数据依赖性。 此外，机制仅将数据存储到系统存储器中，用于仅在确定了数据依赖性的迭代子集中通过迭代执行的存储。 在确定数据相关性的迭代子集中存储由迭代执行的存储数据不会提交给系统存储器。

公开(公告)号：US20100161846A1

公开(公告)日：2010-06-24

申请号：US12342501

申请日：2008-12-23

申请人： Brian K. Flachs ,  Harm P. Hofstee ,  Charles R. Johns ,  Matthew E. King ,  John S. Liberty ,  Brad W. Michael

发明人： Brian K. Flachs ,  Harm P. Hofstee ,  Charles R. Johns ,  Matthew E. King ,  John S. Liberty ,  Brad W. Michael

IPC分类号： G06F3/00

CPC分类号： G06F9/30087 ,  G06F9/3877 ,  G06F13/1663 ,  G06F13/28

摘要： A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

摘要翻译： 提供了编程作为多线程处理器操作的直接存储器访问引擎的机制。 从与直接存储器访问引擎相关联的本地存储器中的主机处理器接收多个程序。 在来自主机处理器的直接存储器访问引擎中接收到指示将要执行位于本地存储器中的多个程序的请求。 直接存储器访问引擎在主机处理器的干预下执行多个程序中的两个或多个。 当多个程序中的两个或更多个程序中的每一个完成执行时，直接存储器访问引擎向主处理器发送指示程序已经完成执行的完成通知。

公开(公告)号：US07711903B2

公开(公告)日：2010-05-04

申请号：US11621315

申请日：2007-01-09

申请人： Michael N. Day ,  Jonathan J. DeMent ,  Charles R. Johns

发明人： Michael N. Day ,  Jonathan J. DeMent ,  Charles R. Johns

IPC分类号： G06F13/00 ,  G06F9/26 ,  G06F12/12

CPC分类号： G06F12/1027 ,  G06F2212/654 ,  G06F2212/684

摘要： A mechanism is provided for efficiently managing the operation of a translation buffer. The mechanism is utilized to pre-load a translation buffer to prevent poor operation as a result of slow warming of a cache. A software pre-load mechanism may be provided for preloading a translation look aside buffer (TLB) via a hardware implemented controller. Following preloading of the TLB, control of accessing the TLB may be handed over to the hardware implemented controller. Upon an application context switch operation, the software preload mechanism may be utilized again to preload the TLB with new translation information for the newly active application instance.

摘要翻译： 提供了一种用于有效地管理翻译缓冲器的操作的机制。 该机制用于预加载翻译缓冲区以防止由于缓存缓慢升温而造成的不良操作。 可以提供软件预加载机制，用于经由硬件实现的控制器来预加载缓冲器（TLB）。 在TLB的预加载之后，可以将访问TLB的控制权交给硬件实现的控制器。 在应用程序上下文切换操作时，可以再次利用软件预载机制来为新活动的应用实例的新的翻译信息预加载TLB。

公开(公告)号：US07600076B2

公开(公告)日：2009-10-06

申请号：US11377506

申请日：2006-03-16

申请人： Charles R. Johns

发明人： Charles R. Johns

IPC分类号： G06F13/00

CPC分类号： G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/526

摘要： A method, system, apparatus, and article of manufacture for performing cacheline polling utilizing store and reserve and load when reservation lost instructions is disclosed. In one embodiment a method is provided which comprises storing a buffer flag busy indicator data value within a first cacheable memory location and setting a load/store operation reservation on said first cacheable memory location via a store and reserve instruction. In the described embodiment, a data value stored within the first cacheable memory location is accessed via a conditional load instruction in response to a determination that the load/store operation reservation on the first cacheable memory location has been reset. Conversely, execution of the conditional load instruction is stalled in response to a determination that the load/store operation reservation on the first cacheable memory location has not been reset.

摘要翻译： 一种方法，系统，装置和制品，用于在公布预约丢失指令时利用存储和预留和加载来执行高速缓存线轮询。 在一个实施例中，提供了一种方法，其包括将缓冲器标志忙指示符数据值存储在第一可缓存存储器位置内，并且经由存储和保留指令在所述第一可缓存存储器位置上设置加载/存储操作预留。 在所描述的实施例中，响应于第一可缓存存储器位置上的加载/存储操作预留被重置的确定，通过条件加载指令来存储存储在第一可缓存存储器位置内的数据值。 相反，响应于对第一可缓存存储器位置的加载/存储操作预留未被重置的确定，条件加载指令的执行被停止。

公开(公告)号：US20090037620A1

公开(公告)日：2009-02-05

申请号：US12127464

申请日：2008-05-27

申请人： Daniel A. Brokenshire ,  Charles R. Johns ,  Mark R. Nutter ,  Barry L. Minor

发明人： Daniel A. Brokenshire ,  Charles R. Johns ,  Mark R. Nutter ,  Barry L. Minor

IPC分类号： G06F3/00

CPC分类号： G06F15/17337

摘要： An apparatus and method for efficient communication of producer/consumer buffer status are provided. With the apparatus and method, devices in a data processing system notify each other of updates to head and tail pointers of a shared buffer region when the devices perform operations on the shared buffer region using signal notification channels of the devices. Thus, when a producer device that produces data to the shared buffer region writes data to the shared buffer region, an update to the head pointer is written to a signal notification channel of a consumer device. When a consumer device reads data from the shared buffer region, the consumer device writes a tail pointer update to a signal notification channel of the producer device. In addition, channels may operate in a blocking mode so that the corresponding device is kept in a low power state until an update is received over the channel.

摘要翻译： 提供了用于生产者/消费者缓冲器状态的有效通信的装置和方法。 利用该设备和方法，当设备使用设备的信号通知通道在共享缓冲区域上执行操作时，数据处理系统中的设备通知彼此对共享缓冲区域的头和尾指针的更新。 因此，当向共享缓冲区域产生数据的生成器设备将数据写入到共享缓冲区域时，对头指针的更新被写入消费者设备的信号通知通道。 当消费者设备从共享缓冲区域读取数据时，消费者设备将尾指针更新写入生成器设备的信号通知通道。 此外，信道可以以阻塞模式操作，使得对应的设备保持在低功率状态，直到通过信道接收到更新。