公开(公告)号：US07176725B2

公开(公告)日：2007-02-13

申请号：US11050895

申请日：2005-02-04

申请人： James W. Dawson ,  Donald W. Plass ,  Kenneth J. Reyer

发明人： James W. Dawson ,  Donald W. Plass ,  Kenneth J. Reyer

IPC分类号： H03K19/094 ,  H03K19/096

CPC分类号： H03K19/0963

摘要： A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage.

摘要翻译： 解码器电路包括具有多个扇入输入的脉冲供电级，由脉冲供电级馈送的动态级，以及通过传递器件选择性地耦合到脉冲供电级的输出节点的复制节点。 通过装置和动态级由时钟信号控制，以便能够利用动态级的时钟启用来对脉冲级的自定时评估。

公开(公告)号：US20070033459A1

公开(公告)日：2007-02-08

申请号：US11180416

申请日：2005-07-13

申请人： Paul A. Bunce ,  John D. Davis ,  Patrick J. Meaney ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Patrick J. Meaney ,  Donald W. Plass

IPC分类号： G01R31/28

CPC分类号： G11C29/48 ,  G01R31/318533 ,  G11C29/88 ,  G11C2029/3202

摘要： A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.

公开(公告)号：US07075855B1

公开(公告)日：2006-07-11

申请号：US11053612

申请日：2005-02-08

申请人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

IPC分类号： G11C8/00

CPC分类号： G11C11/413 ,  G11C7/12 ,  G11C29/846

摘要： An output timing control circuit for use with a memory array. The output timing control circuit includes a redundancy decode circuit and a bit column output circuit. The bit column output circuit includes a first bit column output gate and a second bit column output gate, each bit column output gate is coupled to a bitline in the memory array. A precharge circuit is coupled to an output of the first bit column output gate and the second bit column output gate. The precharge circuit is responsive to a port enable signal. The redundancy decode circuit receives the port enable signal and a fuse signal and activates one of the first bit column output gate and the second bit column output gate.

摘要翻译： 一种与存储器阵列一起使用的输出定时控制电路。 输出定时控制电路包括冗余解码电路和位列输出电路。 位列输出电路包括第一位列输出栅极和第二位列输出栅极，每个位列输出栅极耦合到存储器阵列中的位线。 预充电电路耦合到第一位列输出栅极和第二位列输出栅极的输出端。 预充电电路响应端口使能信号。 冗余解码电路接收端口使能信号和熔丝信号，并激活第一位列输出栅极和第二位列输出栅极之一。

公开(公告)号：US06822885B2

公开(公告)日：2004-11-23

申请号：US10413615

申请日：2003-04-14

申请人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

发明人： Paul A. Bunce ,  John D. Davis ,  Donald W. Plass

IPC分类号： G11C700

CPC分类号： G06F12/0895 ,  G11C7/1006 ,  G11C15/04 ,  G11C2207/104 ,  G11C2207/2245

摘要： A high speed latch and compare function providing rapid cache comparison through the use of a dual rail comparison circuit having transmission gate exclusive or (XOR) circuits.

摘要翻译： 通过使用具有传输门专用或（XOR）电路的双轨比较电路，提供快速缓存比较的高速锁存和比较功能。

公开(公告)号：US08472271B2

公开(公告)日：2013-06-25

申请号：US13030341

申请日：2011-02-18

申请人： James W. Dawson ,  Rajiv V. Joshi ,  Noam Jungmann ,  Elazar Kachir ,  Rouwaida N. Kanj ,  Ehud Nir ,  Donald W. Plass

发明人： James W. Dawson ,  Rajiv V. Joshi ,  Noam Jungmann ,  Elazar Kachir ,  Rouwaida N. Kanj ,  Ehud Nir ,  Donald W. Plass

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/1048 ,  G11C11/413

摘要： Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge source voltage. According to embodiments, the precharge source voltage may be Vdd or Vcs. Optimizing the precharge voltage maximizes memory device performance and functional characteristics, including, but not limited to, stability, efficiency, power, writability, and reliability.

摘要翻译： 本文提供了用于确定最佳存储器件预充电电压的系统和方法。 此外，本文描述了用于提供局部感测放大和电路辅助电路的系统和方法。 实施例提供了用于确定预充电乘法器，其可以用于基于预充电源电压来确定最佳预充电电压。 根据实施例，预充电源电压可以是Vdd或Vcs。 优化预充电电压使存储器件性能和功能特性最大化，包括但不限于稳定性，效率，功率，写入性和可靠性。

公开(公告)号：US20120213023A1

公开(公告)日：2012-08-23

申请号：US13030341

申请日：2011-02-18

申请人： James W. Dawson ,  Rajiv V. Joshi ,  Noam Jungmann ,  Elazar Kachir ,  Rouwaida N. Kanj ,  Ehud Nir ,  Donald W. Plass

发明人： James W. Dawson ,  Rajiv V. Joshi ,  Noam Jungmann ,  Elazar Kachir ,  Rouwaida N. Kanj ,  Ehud Nir ,  Donald W. Plass

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C7/1048 ,  G11C11/413

摘要： Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge source voltage. According to embodiments, the precharge source voltage may be Vdd or Vcs. Optimizing the precharge voltage maximizes memory device performance and functional characteristics, including, but not limited to, stability, efficiency, power, writability, and reliability.

摘要翻译： 本文提供了确定最佳存储器件预充电电压的系统和方法。 此外，本文描述了用于提供局部感测放大和电路辅助电路的系统和方法。 实施例提供了用于确定预充电乘法器，其可以用于基于预充电源电压来确定最佳预充电电压。 根据实施例，预充电源电压可以是Vdd或Vcs。 优化预充电电压使存储器件性能和功能特性最大化，包括但不限于稳定性，效率，功率，写入性和可靠性。

公开(公告)号：US07953987B2

公开(公告)日：2011-05-31

申请号：US11682349

申请日：2007-03-06

申请人： Carl U. Buscaglia ,  Vincenzo Condorelli ,  Kevin C. Gotze ,  Nihad Hadzic ,  Donald W. Plass ,  Tamas Visegrady

发明人： Carl U. Buscaglia ,  Vincenzo Condorelli ,  Kevin C. Gotze ,  Nihad Hadzic ,  Donald W. Plass ,  Tamas Visegrady

IPC分类号： G06F12/14

CPC分类号： G06F21/86 ,  G06F2221/2143

摘要： A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn-in in secure electronic modules. Sequentially storing the data and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area.

摘要翻译： 公开了一种用于防止由安全电子模块中的优选状态/老化引起的秘密数据的意外保留的方法和装置。 在交替的时钟周期内顺序存储数据及其反相，并通过主动覆盖数据来破坏数据，从而防止SRAM器件发展成优先状态。 通过使用主加密密钥加密相对大量的秘密数据，并将所述主密钥存储在该非优选状态存储器中，电子模块便于将该保护方案扩展到大量的数据，而无需投入或主动地开销 擦除较大的存储区域。

公开(公告)号：US07793173B2

公开(公告)日：2010-09-07

申请号：US12164869

申请日：2008-06-30

申请人： Tom Y. Chang ,  William V. Huott ,  Thomas J. Knips ,  Donald W. Plass

发明人： Tom Y. Chang ,  William V. Huott ,  Thomas J. Knips ,  Donald W. Plass

IPC分类号： G11C29/00

CPC分类号： G11C29/24 ,  G11C11/41 ,  G11C29/44 ,  G11C2029/0401 ,  G11C2029/1208 ,  G11C2029/4402

摘要： Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.

摘要翻译： 使用包括简单数据历史表在内的自检内置阵列。 该表用于跟踪在处理器或逻辑半导体芯片的任何级别的组装测试期间观察到的故障位置，其中芯片包含具有用于故障消除的冗余元件的SRAM宏。

公开(公告)号：US07787284B2

公开(公告)日：2010-08-31

申请号：US12133450

申请日：2008-06-05

申请人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

发明人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C11/412 ,  G11C11/417

摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

摘要翻译： 可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。 阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。 正常基极FET具有基极阈值，并且定制的FET具有高于阈值。 在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

公开(公告)号：US07688650B2

公开(公告)日：2010-03-30

申请号：US12139675

申请日：2008-06-16

申请人： John D. Davis ,  Paul A. Bunce ,  Donald W. Plass ,  Kenneth J. Reyer

发明人： John D. Davis ,  Paul A. Bunce ,  Donald W. Plass ,  Kenneth J. Reyer

IPC分类号： G11C7/00 ,  G11C7/22

CPC分类号： G11C11/413 ,  G11C7/18

摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.

摘要翻译： 为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。 写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。 选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。 至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。 在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。