公开(公告)号：US20070018278A1

公开(公告)日：2007-01-25

申请号：US11189098

申请日：2005-07-25

申请人： Michael Kund ,  Josef Willer

发明人： Michael Kund ,  Josef Willer

IPC分类号： H01L29/00

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： The channel regions (T) of the memory cells are directed transversly to the word lines (2), which are arranged parallel at a distance from one another. Local interconnects (6) connect the source/drain regions of the memory cell transistors to bit lines running across the word lines and are connected to local interconnects in every next but one interspace between neighboring word lines. Every local interconnect is connected to only one source/drain region, which is enabled by enlarged shallow trench isolations (7) between the active areas. This memory cell array allows an individual programming and erasing of every single cell and can be integrated with a flash memory array comprising local interconnects and upper bit lines and is intended for file storage.

摘要翻译： 存储单元的通道区域（T）被横向地引导到彼此相隔一定距离并排布置的字线（2）。 本地互连（6）将存储单元晶体管的源极/漏极区域连接到跨过字线延伸的位线，并且在相邻字线之间的每个下一个但是一个间隔中连接到局部互连。 每个局部互连仅连接到一个源极/漏极区域，其通过在有源区域之间扩大的浅沟槽隔离（7）来实现。 该存储单元阵列允许单个单元的单独编程和擦除，并且可以与包括本地互连和高位线的闪存阵列集成，并且用于文件存储。

公开(公告)号：US06998672B2

公开(公告)日：2006-02-14

申请号：US10779557

申请日：2004-02-06

申请人： Franz Hofmann ,  Josef Willer

发明人： Franz Hofmann ,  Josef Willer

IPC分类号： H01L29/788

CPC分类号： H01L29/7923

摘要： A memory cell having a source region, a drain region, a source-end control gate, a drain-end control gate, an injection gate arranged between the source-end control gate and the drain-end control gate, a source-end storage element arranged in the source-end control gate, and a drain-end storage element arranged in the drain-end control gate. To program the memory cell, a low electrical voltage is applied to the injection gate, and a high electrical voltage is applied to the control gates.

摘要翻译： 具有源极区域，漏极区域，源极端子控制栅极，漏极端子控制栅极，配置在源极端子控制栅极和漏极端子控制栅极之间的注入栅极的存储单元，源极端子存储器 排列在源极端控制栅极中的漏极端存储元件，以及布置在漏极端控制栅极中的漏极端存储元件。 为了对存储单元进行编程，将低电压施加到注入栅极，并且高电压被施加到控制栅极。

公开(公告)号：US20050196922A1

公开(公告)日：2005-09-08

申请号：US10795611

申请日：2004-03-08

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/105

CPC分类号： H01L27/105 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573

摘要： The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.

摘要翻译： 本发明提供了一种用于存储单元阵列，特别是电荷捕获存储单元阵列的集成方案，其包括局部互连的架构，其能够避免字线堆叠的氮化物绝缘并且在标准技术中产生不同结构和尺寸的CMOS器件 以及更高级的存储单元晶体管。

公开(公告)号：US06913987B2

公开(公告)日：2005-07-05

申请号：US10728388

申请日：2003-12-05

申请人： Juerg Haufe ,  Josef Willer

发明人： Juerg Haufe ,  Josef Willer

IPC分类号： H01L21/283 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L27/11568 ,  H01L21/76897 ,  H01L27/115

摘要： Word lines of a semiconductor component are provided with an encapsulation of dielectric material, Spacers of oxide extend alongside at the sidewalls of the word lines. The spacers are subsequently covered together with the word lines with a nitride layer. Borophosporosilicate glass is introduced between those portions of the nitride layer which respectively belong to a word line and is removed selectively with respect to the nitride using a mask. Contact hole fillings for the electrical connection of the buried bit lines are introduced into the contact holes thus formed.

摘要翻译： 半导体元件的字线被提供有电介质材料的封装，氧化物隔离物在字线的侧壁旁边延伸。 间隔物随后用氮化物层与字线一起被覆盖。 硼氮硅玻璃被引入到分别属于字线的氮化物层的这些部分之间并且使用掩模相对于氮化物被选择性地去除。 将掩埋位线的电连接的接触孔填充物引入由此形成的接触孔中。

公开(公告)号：US20050067659A1

公开(公告)日：2005-03-31

申请号：US10916013

申请日：2004-08-11

申请人： Martin Gutsche ,  Josef Willer ,  Cay-Uwe Pinnow ,  Ralf Symanczyk

发明人： Martin Gutsche ,  Josef Willer ,  Cay-Uwe Pinnow ,  Ralf Symanczyk

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42332

摘要： The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).

摘要翻译： 存储层（6）在每种情况下都存在于沟道区域（3）邻接源极/漏极区域（2）的区域上方，并且在每个情况下都被中断在沟道区域（3）的中间部分之上。 存储层（6）由栅极电介质（4）的材料形成，并且包含通过离子注入引入的硅或锗纳米晶体或纳米点。 栅电极（5）通过导电间隔物（7）在侧面加宽。

公开(公告)号：US06844584B2

公开(公告)日：2005-01-18

申请号：US09927573

申请日：2001-08-09

申请人： Herbert Palm ,  Josef Willer ,  Achim Gratz ,  Jakob Kriz ,  Mayk Roehrich

发明人： Herbert Palm ,  Josef Willer ,  Achim Gratz ,  Jakob Kriz ,  Mayk Roehrich

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.

摘要翻译： 每个存储单元是存储晶体管，其设置在半导体本体的顶侧，并且具有布置在形成于半导体材料中的源极区域和漏极区域之间的沟槽中的栅电极。 栅电极通过介电材料与半导体材料分离。 至少在源极区域和栅极电极之间以及漏极区域和栅极电极之间，存在氧化物 - 氧化物 - 氧化物层序列。 层序列是为了在源极和漏极处俘获电荷载体而提供的。

公开(公告)号：US06686242B2

公开(公告)日：2004-02-03

申请号：US09917867

申请日：2001-07-26

申请人： Josef Willer ,  Ronald Kakoschke

发明人： Josef Willer ,  Ronald Kakoschke

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

摘要： A method for producing bit lines for a memory cell array comprises as a first step the step of providing a layer structure which comprises a substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on the surface of said substrate, and a gate region layer provided on said sequence of storage medium layers. Bit line recesses, which extend down to the sequence of storage medium layers, are produced in said gate region layer. Subsequently, insulating spacer layers are produced on lateral surfaces of said bit line recesses, whereupon a source/drain implantation is executed in the area of said bit line recesses, after a complete or partial removal of the sequence of storage medium layers. Following this, the substrate is exposed completely in the area of the bit line recesses, if this has not yet been done prior to the implantation. Subsequently, metallizations for producing metallic bit lines are produced on the exposed substrate, said metallizations being insulated from the gate region layer by the insulating spacer layers.

摘要翻译： 一种用于产生存储单元阵列的位线的方法包括作为第一步骤的步骤，提供包括在其表面上注入晶体管阱的衬底的层结构，设置在所述衬底的表面上的一系列存储介质层， 以及设置在所述存储介质层序列上的栅极区域层。 在所述栅极区域层中产生向下延伸到存储介质层序列的位线凹槽。 随后，在所述位线凹槽的侧表面上产生绝缘间隔层，于是在完成或部分去除存储介质层序列之后，在所述位线凹槽的区域中执行源极/漏极注入。 接下来，如果在植入之前还没有完成，则衬底完全暴露在位线凹槽的区域中。 随后，在暴露的基板上制造用于制造金属位线的金属化，所述金属化通过绝缘间隔层与栅极​​区域层绝缘。

公开(公告)号：US06661053B2

公开(公告)日：2003-12-09

申请号：US10022654

申请日：2001-12-18

申请人： Josef Willer ,  Frank Lau ,  Dezsö Takacs

发明人： Josef Willer ,  Frank Lau ,  Dezsö Takacs

IPC分类号： H01L2976

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/78

摘要： A memory cell includes a storage transistor having the following structure and being dimensioned to shorten program and erase times. A semiconductor body includes a top surface and a trench formed therein having walls joined by a curved bottom. A source zone in the semiconductor body is doped from the top surface. A drain zone in the semiconductor body is doped from the top surface. Junctions of the source and drain zones are beneath each. A gate electrode on the top surface of the semiconductor body is disposed between the source zone and the drain zone in the trench. A dielectric layer isolates the gate electrode from the semiconductor body and acts as a storage medium. Each of the junctions intersects a respective one of the walls at a respective depth from the bottom. A respective spacing across the trench is defined at each depth.

摘要翻译： 存储单元包括具有以下结构的存储晶体管，其尺寸被设计为缩短编程和擦除时间。 半导体本体包括顶表面和形成在其中的具有由弯曲底部连接的壁的沟槽。 半导体本体中的源区从顶表面掺杂。 半导体本体中的漏极区域从上表面掺杂。 源极和漏极区的接合点在每个下方。 半导体本体的顶表面上的栅电极设置在沟槽中的源区和漏区之间。 电介质层将栅电极与半导体本体隔离并用作存储介质。 每个连接点在与底部相应的深度处与相应的一个壁相交。 在每个深度处限定跨沟槽的相应间隔。

公开(公告)号：US06576948B2

公开(公告)日：2003-06-10

申请号：US09873231

申请日：2001-06-04

申请人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

发明人： Franz Hofmann ,  Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L27108

CPC分类号： H01L27/108

摘要： An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.

摘要翻译： 集成电路包含平面第一晶体管和二极管。 二极管连接在第一晶体管的第一源极/漏极区域和第一晶体管的栅电极之间，使得电荷被阻止从栅电极放电到第一源极/漏极区域。 作为二极管的一部分的二极管层设置在第一源极/漏极区域的一部分上。 作为二极管的附加部分的导电结构设置在栅电极的一部分上方并且设置在二极管层上。 二极管可以配置为隧道二极管。 二极管层可以通过热氧化生产。 制造二极管只需要一个掩模。 电容器可以设置在二极管的上方。 电容器的第一电容器电极连接到导电结构。

公开(公告)号：US06521935B2

公开(公告)日：2003-02-18

申请号：US10027524

申请日：2001-12-26

申请人： Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

发明人： Wolfgang Krautschneider ,  Till Schlösser ,  Josef Willer

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7841 ,  H01L29/78642

摘要： A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.

摘要翻译： MOS晶体管包括上层堆叠的上源极/漏极区，沟道区和下源极/漏极区，并且形成衬底的突起。 栅极电介质邻接突起的第一横向区域。 栅电极邻接栅极电介质。 导电结构在通道区域的区域中毗邻突起的第二横向区域。 导电结构邻接栅电极。