公开(公告)号：US20080211012A1

公开(公告)日：2008-09-04

申请号：US12114575

申请日：2008-05-02

申请人： Christopher Boguslaw Kocon ,  Praveen Muraleedharan Shenoy

发明人： Christopher Boguslaw Kocon ,  Praveen Muraleedharan Shenoy

IPC分类号： H01L49/00 ,  H01L21/335

CPC分类号： H01L29/7804 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L29/7838 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01078 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00

摘要： An accumulation-mode field effect transistor includes a drift region of a first conductivity type, channel regions of the first conductivity type over and in contact with the drift region, and gate trenches having sidewalls abutting the channel regions. The gate trenches extend into and terminate within the drift region. The transistor further includes a first plurality of silicon regions of a second conductivity type forming P-N junctions with the channel regions along vertical walls of the first plurality of silicon regions. The first plurality of silicon regions extend into the drift region and form P-N junctions with the drift region along bottoms of the first plurality of silicon regions.

摘要翻译： 累积模式场效应晶体管包括第一导电类型的漂移区域，第一导电类型的沟道区域，并且与漂移区域接触并且与漂移区域接触，栅极沟槽具有邻接沟道区域的侧壁。 栅极沟槽延伸到漂移区域并终止于漂移区域内。 晶体管还包括第一导电类型的第一多个硅区域，其形成与沿着第一多个硅区域的垂直壁的沟道区域的P-N结。 第一多个硅区域延伸到漂移区域中，并沿着第一多个硅区域的底部与漂移区域形成P-N结。

公开(公告)号：US07265415B2

公开(公告)日：2007-09-04

申请号：US10962367

申请日：2004-10-08

申请人： Praveen Muraleedharan Shenoy ,  Christopher Boguslaw Kocon

发明人： Praveen Muraleedharan Shenoy ,  Christopher Boguslaw Kocon

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

摘要： In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

摘要翻译： 在本发明的一个实施例中，沟槽MOS门控晶体管包括形成具有第二导电类型的阱区的pn结的第一导电类型的第一区域。 阱区域具有平坦的底部部分和比平坦的底部部分更深的部分。 栅极沟槽延伸到阱区域中。 通道区域沿着栅极沟槽的外侧壁在阱区域中延伸。 栅极沟槽具有终止于第一区域内的第一底部部分和终止于阱区域较深部分内的第二底部部分，使得当晶体管处于导通状态时，阱区域的较深部分防止电流 从而流过位于井区域较深部分正上方的那些通道区域部分。