Forming integrated circuits using selective deposition of undoped silicon film seeded in chlorine and hydride gas
    24.
    发明授权
    Forming integrated circuits using selective deposition of undoped silicon film seeded in chlorine and hydride gas 失效
    使用选择性沉积接入氯和氢化物气体的未掺杂硅膜形成集成电路

    公开(公告)号:US07229890B2

    公开(公告)日:2007-06-12

    申请号:US10368069

    申请日:2003-02-18

    IPC分类号: H01L21/20

    摘要: A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using this process, followed by an anneal to create hemishperical grain (HSG) polysilicon. Multilayer capacitor containers are formed in a non-oxidizing ambient so that no oxide is formed between the layers. The structure formed is planarized to form separate containers made from doped and undoped amorphous silicon layers. Selected ones of undoped layers are seeded in a chlorine containing environment and annealed to form HSG. A dielectric layer and second electrode are formed to complete the cell capacitor.

    摘要翻译: 通过在膜的形成期间流动氯,形成具有增强的选择性的多晶硅膜。 氯作为蚀刻剂,其邻近多晶硅结构的绝缘区域需要形成薄膜。 使用该方法形成用于电容器的底部电极,随后进行退火以产生半透明晶粒(HSG)多晶硅。 多层电容器容器形成在非氧化环境中,使得在层之间不形成氧化物。 所形成的结构被平坦化以形成由掺杂和未掺杂的非晶硅层制成的分离的容器。 将选定的未掺杂层接种在含氯环境中并退火以形成HSG。 形成电介质层和第二电极以完成电池电容器。

    Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same
    28.
    发明授权
    Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same 有权
    具有可调栅电极功能的双金属CMOS晶体管及其制作方法

    公开(公告)号:US07078278B2

    公开(公告)日:2006-07-18

    申请号:US10833073

    申请日:2004-04-28

    IPC分类号: H01L28/80

    摘要: A dual-metal CMOS arrangement and method of making the same provides a substrate and a plurality of NMOS devices and PMOS devices formed on the substrate. Each of the plurality of NMOS devices and PMOS devices have gate electrodes. Each NMOS gate electrode includes a first silicide region on the substrate and a first metal region on the first silicide region. The first silicide region of the NMOS gate electrode consists of a first silicide having a work function that is close to the conduction band of silicon. Each of the PMOS gate electrodes includes a second silicide region on the substrate and a second metal region on the second silicide region. The second silicide region of the PMOS gate electrode consists of a second silicide having a work function that is close to the valence band of silicon.

    摘要翻译: 双金属CMOS布置及其制造方法提供了形成在衬底上的衬底和多个NMOS器件和PMOS器件。 多个NMOS器件和PMOS器件中的每一个具有栅电极。 每个NMOS栅极包括衬底上的第一硅化物区域和第一硅化物区域上的第一金属区域。 NMOS栅电极的第一硅化物区域由具有接近硅导带的功函数的第一硅化物组成。 每个PMOS栅极电极包括衬底上的第二硅化物区域和第二硅化物区域上的第二金属区域。 PMOS栅电极的第二硅化物区域由具有接近硅的价带的功函数的第二硅化物组成。

    UCP4
    29.
    发明申请
    UCP4 有权

    公开(公告)号:US20060068439A1

    公开(公告)日:2006-03-30

    申请号:US11265966

    申请日:2005-11-03

    摘要: The present invention is directed to novel polypeptides having homology to certain human uncoupling proteins (“UCPs”) and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention, and methods for producing the polypeptides of the present invention.

    摘要翻译: 本发明涉及与某些人解偶联蛋白(“UCP”)和编码那些多肽的核酸分子具有同源性的新型多肽。 本文还提供了包含那些核酸序列的载体和宿主细胞,包含与异源多肽序列融合的本发明多肽的嵌合多肽分子,与本发明的多肽结合的抗体,以及本发明多肽的制备方法 发明。

    Dual metal CMOS transistors with silicon-metal-silicon stacked gate electrode
    30.
    发明授权
    Dual metal CMOS transistors with silicon-metal-silicon stacked gate electrode 有权
    双金属CMOS晶体管与硅 - 金属硅堆叠栅电极

    公开(公告)号:US07018887B1

    公开(公告)日:2006-03-28

    申请号:US10788281

    申请日:2004-03-01

    申请人: James Pan

    发明人: James Pan

    IPC分类号: H01L21/8238

    CPC分类号: H01L21/823842

    摘要: A method of forming dual metal CMOS transistors includes forming a first silicon layer on a gate dielectric layer provided on a substrate. A first metal layer is formed on the NMOS device areas. A second metal layer is formed on the PMOS device areas. These first and second metal layers consist of different metals. A second silicon layer is deposited on the first and second metal layers. A dry etching technique is performed to etch the second silicon layer, the first and second metal layers, and the first silicon layer. The dry etching stops on the gate dielectric layer, thereby forming gate electrodes. The first and second metal layers are reacted with the first and second silicon layers to form suicides in the gate electrodes.

    摘要翻译: 形成双金属CMOS晶体管的方法包括在设置在基板上的栅介质层上形成第一硅层。 在NMOS器件区域上形成第一金属层。 在PMOS器件区域上形成第二金属层。 这些第一和第二金属层由不同的金属组成。 第二硅层沉积在第一和第二金属层上。 执行干蚀刻技术以蚀刻第二硅层,第一和第二金属层以及第一硅层。 干蚀刻停止在栅介质层上,从而形成栅电极。 第一和第二金属层与第一和第二硅层反应,以在栅电极中形成自杀。