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公开(公告)号：US20120127193A1
公开(公告)日：2012-05-24
申请号：US12950267
申请日：2010-11-19
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
摘要： A display pipe may include fetch circuitry and a scaler unit, and registers programmable with information that defines active regions of an image frame. Pixels within the active regions are active pixels to be displayed, pixels outside of the active regions are inactive pixels not to be displayed. The fetch circuitry may retrieve frames from memory, retrieving the active pixels and not retrieving the inactive pixels as defined by the programmed contents of the registers. A scaler unit may produce scaled pixels from the fetched pixels, basing each scaled pixel on a respective corresponding set of pixels. When a given pixel of the respective corresponding set of pixels is an inactive pixel, the scaler unit may assign an estimated value to the given pixel based on one or more active pixels in the respective corresponding set of pixels. The scaler unit may provide the scaled pixels to a blend unit for blending with other pixels.
摘要翻译： 显示管可以包括提取电路和缩放器单元，并且可以用定义图像帧的有效区域的信息来编程。 活动区域内的像素是要显示的活动像素，活动区域之外的像素是不显示的不活动像素。 提取电路可以从存储器检索帧，检索有效像素，而不检索由寄存器的编程内容定义的非活动像素。 缩放器单元可以从获取的像素产生缩放的像素，将每个缩放的像素基于相应的相应的像素集。 当相应的相应像素集合的给定像素是非活动像素时，缩放器单元可以基于相应的相应像素集合中的一个或多个有效像素来分配给定像素的估计值。 缩放器单元可以将缩放的像素提供给用于与其他像素混合的混合单元。
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公开(公告)号：US20120127187A1
公开(公告)日：2012-05-24
申请号：US12950239
申请日：2010-11-19
IPC分类号： G09G5/36
CPC分类号： G09G5/397 , G09G5/36 , G09G2330/12 , G09G2340/0407 , G09G2340/06 , G09G2340/10 , G09G2340/125 , G09G2360/10 , G09G2360/125
摘要： Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available. The results generated by the error-checking may be read and compared to an expected value to detect test pass/fail conditions.
摘要翻译： 视频显示管道可以用FIFO（先进先出）缓冲器终止，从而将像素提供给显示控制器以在图形/视频显示器上显示像素。 显示管道可以以比显示控制器从FIFO缓冲器提取像素的速率高得多的速率来频繁地处理像素。 在仅错误检查模式中，FIFO可以被禁用，并且连接在FIFO前面的错误校验（例如CRC）块可以像显示管能够处理显示管一样快地接收由显示管处理的像素 像素。 因此，执行测试所需的测试/模拟时间的长度可以由生成像素的速率而不是显示控制器显示像素的速率来确定。 在不支持显示或不可用的环境中也可以进行测试/模拟。 可以读取错误检查产生的结果并将其与期望值进行比较，以检测测试通过/失败条件。
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23.发明申请IMAGE SENSOR DATA FORMATS AND MEMORY ADDRESSING TECHNIQUES FOR IMAGE SIGNAL PROCESSING 有权用于图像信号处理的图像传感器数据格式和存储器寻址技术公开(公告)号：US20120081577A1
公开(公告)日：2012-04-05
申请号：US12895346
申请日：2010-09-30
IPC分类号： H04N5/76
CPC分类号： H04N5/772 , H04N5/23229 , H04N5/23235 , H04N5/2354 , H04N5/3572 , H04N5/367 , H04N9/045 , H04N9/735 , H04N19/80
摘要： Certain embodiments of the present disclosure provide a flexible memory input/output controller that is configured to the storing and reading of multiple types of pixels and pixel memory formats. For instance, the memory I/O controller may support the storing and reading of raw image pixels at various bits of precision, such as 8-bit, 10-bit, 12-bit, 14-bit, and 16-bit. Pixel formats that are unaligned with memory bytes (e.g., not being a multiple of 8-bits) may be stored in a packed manner. The memory I/O controller may also support various formats of RGB pixel sets and YCC pixel sets.
摘要翻译： 本公开的某些实施例提供了一种灵活的存储器输入/输出控制器，其被配置为存储和读取多种类型的像素和像素存储器格式。 例如，存储器I / O控制器可以支持以各种精度位（例如8位，10位，12位，14位和16位）存储和读取原始图像像素。 与存储器字节不对齐的像素格式（例如，不是8位的倍数）可以以打包的方式存储。 存储器I / O控制器还可以支持RGB像素集和YCC像素集的各种格式。
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公开(公告)号：US06597363B1
公开(公告)日：2003-07-22
申请号：US09378637
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
IPC分类号： G06T120
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.
摘要翻译： 描述了包括许多子结构的图形处理器和方法，包括专用子系统，子处理器，设备，架构和相应的过程。 本发明的实施例可以包括延迟着色，出血帧缓冲器和多级隐藏表面去除处理以及其他结构和/或程序中的一个或多个。 本发明的实施例被设计为提供具有Phong着色，子像素抗锯齿，纹理和凹凸映射的高性能3D图形。
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公开(公告)号：US20150296193A1
公开(公告)日：2015-10-15
申请号：US13484814
申请日：2012-05-31
申请人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Steven David Hordley , Joseph P. Bratt
发明人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Steven David Hordley , Joseph P. Bratt
CPC分类号： H04N9/646 , G06T1/20 , G06T3/4015 , G06T5/002 , G06T5/009 , G06T5/20 , G06T2207/10024 , H04N5/365 , H04N9/045 , H04N9/735
摘要： Systems and methods for processing image data in RGB format are provided. In one example, an electronic device includes memory to store image data in raw or RGB format, or both, and an RGB image processing pipeline to process the image data. Specifically, the RGB image processing pipeline may process the image data regardless of whether the image data is of raw or RGB format. The RGB image processing pipeline may include receiving logic to receive the image data in raw or RGB format and demosaicing logic to, when the receiving logic receives the image data in raw format, convert the image data into RGB format. The logic may include local tone mapping logic configured to apply spatially varying tone curves to the image data, a color correction matrix configured to correct color in the image data, and gamma logic configured to transform the image data into gamma space.
摘要翻译： 提供了以RGB格式处理图像数据的系统和方法。 在一个示例中，电子设备包括用于以原始或RGB格式或两者存储图像数据的存储器和用于处理图像数据的RGB图像处理流水线。 具体而言，RGB图像处理流水线可以处理图像数据，而不管图像数据是原始还是RGB格式。 RGB图像处理流水线可以包括接收逻辑以接收原始或RGB格式的图像数据和去马赛克逻辑，当接收逻辑以原始格式接收图像数据时，将图像数据转换为RGB格式。 逻辑可以包括被配置为将空间变化的色调曲线应用于图像数据的本地色调映射逻辑，配置为校正图像数据中的颜色的色彩校正矩阵，以及被配置为将图像数据变换为伽马空间的伽马逻辑。
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公开(公告)号：US09105078B2
公开(公告)日：2015-08-11
申请号：US13485421
申请日：2012-05-31
申请人： Suk Hwan Lim , D. Amnon Silverstein , Guy Cote , Steven David Hordley , Graham Finlayson , Weichun Ku , Joseph P. Bratt
发明人： Suk Hwan Lim , D. Amnon Silverstein , Guy Cote , Steven David Hordley , Graham Finlayson , Weichun Ku , Joseph P. Bratt
CPC分类号： G06T5/001 , G06K9/38 , G06T1/20 , G06T5/002 , G06T5/003 , G06T5/008 , G06T5/50 , G06T2207/10024 , G06T2207/20012 , G06T2207/20028 , G06T2207/20208
摘要： Systems and methods for local tone mapping are provided. In one example, an electronic device includes an electronic display, an imaging device, and an image signal processor. The electronic display may display images of a first bit depth, and the imaging device may include an image sensor that obtains image data of a higher bit depth than the first bit depth. The image signal processor may process the image data, and may include local tone mapping logic that may apply a spatially varying local tone curve to a pixel of the image data to preserve local contrast when displayed on the display. The local tone mapping logic may smooth the local tone curve applied to the intensity difference between the pixel and another nearby pixel exceeds a threshold.
摘要翻译： 提供了本地色调映射的系统和方法。 在一个示例中，电子设备包括电子显示器，成像设备和图像信号处理器。 电子显示器可以显示第一位深度的图像，并且成像装置可以包括获得比第一位深度更高的位深度的图像数据的图像传感器。 图像信号处理器可以处理图像数据，并且可以包括本地色调映射逻辑，其可以将空间上变化的本地色调曲线应用于图像数据的像素，以便在显示器上显示时保持局部对比度。 本地色调映射逻辑可以平滑应用于像素和另一附近像素之间的强度差超过阈值的局部色调曲线。
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公开(公告)号：US09077943B2
公开(公告)日：2015-07-07
申请号：US13484741
申请日：2012-05-31
申请人： Suk Hwan Lim , D. Amnon Silverstein , Guy Cote , Steven David Hordley , Graham Finlayson , Weichun Ku , Joseph P. Bratt
发明人： Suk Hwan Lim , D. Amnon Silverstein , Guy Cote , Steven David Hordley , Graham Finlayson , Weichun Ku , Joseph P. Bratt
CPC分类号： H04N9/73 , H04N5/142 , H04N9/045 , H04N9/735 , H04N2209/046
摘要： Systems and methods for generating local image statistics are provided. In one example, an image signal processing system may include a statistics pipeline with image processing logic and local image statistics collection logic. The image processing logic may receive and process pixels of raw image data. The local image statistics collection logic may generate a local histogram associated with a luminance of the pixels of a first block of pixels of the raw image data or a thumbnail in which a pixel of the thumbnail represents a downscaled version of the luminance of the pixels of the first block of the pixel. The raw image data may include many other blocks of pixels of the same size as the first block of pixels.
摘要翻译： 提供了生成本地图像统计信息的系统和方法。 在一个示例中，图像信号处理系统可以包括具有图像处理逻辑和本地图像统计信息收集逻辑的统计流水线。 图像处理逻辑可以接收和处理原始图像数据的像素。 本地图像统计收集逻辑可以生成与原始图像数据的第一像素块的像素的亮度相关联的局部直方图或缩略图，其中缩略图的像素表示缩略图的像素的亮度 像素的第一个块。 原始图像数据可以包括与第一像素块相同尺寸的许多其他像素块。
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公开(公告)号：US09032113B2
公开(公告)日：2015-05-12
申请号：US12057146
申请日：2008-03-27
CPC分类号： G06F13/34 , G06F1/12 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3287 , G06F13/1673 , G06F13/28 , Y02D10/126 , Y02D10/151 , Y02D10/171
摘要： A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer.
摘要翻译： 公开了一种利用DMA控制器访问I / O和存储器件的方法和系统。 每个设备可以通过单独的通道连接到DMA控制器。 DMA中的时钟电路可以允许DMA控制器以规定的频率向每个设备发送信号。 此外，DMA控制器能够基于各个设备的操作状态来激活和去激活用于向设备发送信号的通道时钟。 DMA控制器还能够根据任何有源器件的功能调整通道时钟。 以这种方式，DMA数据传输期间使用的带宽量可以根据与数据传输相关的设备的具体要求进行调整。
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公开(公告)号：US09025867B2
公开(公告)日：2015-05-05
申请号：US13484926
申请日：2012-05-31
申请人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Simon Wolfenden Butler , Mark A. Zimmer , Joseph P. Bratt
发明人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Simon Wolfenden Butler , Mark A. Zimmer , Joseph P. Bratt
CPC分类号： G06T1/20 , G06T3/4015
摘要： Systems and methods for processing YCC image data provided. In one example, an electronic device includes memory to store image data in RGB or YCC format and a YCC image processing pipeline to process the image data. The YCC image processing pipeline may include receiving logic configured to receive the image data in RGB or YCC format and color space conversion logic configured to, when the image data is received in RGB format, convert the image data into YCC format. The YCC image processing logic may also include luma sharpening and chroma suppression logic; brightness, contrast, and color adjustment logic; gamma logic; chroma decimation logic; scaling logic; and chroma noise reduction logic.
摘要翻译： 用于处理提供的YCC图像数据的系统和方法。 在一个示例中，电子设备包括以RGB或YCC格式存储图像数据的存储器和用于处理图像数据的YCC图像处理流水线。 YCC图像处理流水线可以包括被配置为接收RGB或YCC格式的图像数据的接收逻辑，以及配置为当以RGB格式接收图像数据时将图像数据转换为YCC格式的颜色空间转换逻辑。 YCC图像处理逻辑还可以包括亮度锐化和色度抑制逻辑; 亮度，对比度和颜色调整逻辑; 伽玛逻辑; 色度抽取逻辑; 缩放逻辑; 和色度降噪逻辑。
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公开(公告)号：US20130321675A1
公开(公告)日：2013-12-05
申请号：US13485024
申请日：2012-05-31
CPC分类号： H04N9/64 , H04N5/23212 , H04N5/23229 , H04N5/23254 , H04N5/365 , H04N5/367 , H04N9/045
摘要： Systems and methods for down-scaling are provided. In one example, a method for processing image data includes determining a plurality of output pixel locations using a position value stored by a position register, using the current position value to select a center input pixel from the image data and selecting an index value, selecting a set of input pixels adjacent to the center input pixel, selecting a set of filtering coefficients from a filter coefficient lookup table using the index value, filtering the set of source input pixels to apply a respective one of the set of filtering coefficients to each of the set of source input pixels to determine an output value for the current output pixel at the current position value, and correcting chromatic aberrations in the set of source input pixels.
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