公开(公告)号：US07148526B1

公开(公告)日：2006-12-12

申请号：US10348758

申请日：2003-01-23

申请人： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

发明人： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L29/72

CPC分类号： H01L29/7855 ,  H01L21/823821 ,  H01L29/42384 ,  H01L29/7843 ,  H01L29/78684

摘要： A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.

摘要翻译： 双栅极锗金属氧化物半导体场效应晶体管（MOSFET）包括锗翅片，邻近锗翅片的第一侧形成的第一栅极和与第一侧相对的锗翅片第二侧附近形成的第二栅极 。 三栅极MOSFET包括锗翅片，与锗翅片的第一侧相邻形成的第一栅极，与第一侧相对的锗翅片的第二侧附近形成的第二栅极和形成在锗翅片顶部上的顶栅极 。 全栅极MOSFET包括锗翅片，邻近锗翅片的第一侧形成的第一侧壁栅极结构，邻近锗翅片的第二侧形成的第二侧壁栅极结构，以及形成在锗翅片上和周围的附近的栅极结构 锗鳍

公开(公告)号：US06853020B1

公开(公告)日：2005-02-08

申请号：US10290330

申请日：2002-11-08

申请人： Bin Yu ,  Judy Xilin An

发明人： Bin Yu ,  Judy Xilin An

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/80

CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7856 ,  H01L29/78684 ,  Y10S257/90

摘要： A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is located on one side of the fin. A portion of the first gate includes conductive material doped with an n-type dopant. The second gate is formed on the insulating layer and is located on the opposite side of the fin as the first gate. A portion of the second gate includes conductive material doped with a p-type dopant.

摘要翻译： 双栅半导体器件包括衬底，绝缘层，鳍和两个栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 第一栅极形成在绝缘层上并且位于鳍的一侧。 第一栅极的一部分包括掺杂有n型掺杂剂的导电材料。 第二栅极形成在绝缘层上，并且位于作为第一栅极的鳍片的相对侧上。 第二栅极的一部分包括掺杂有p型掺杂剂的导电材料。

公开(公告)号：US06803631B2

公开(公告)日：2004-10-12

申请号：US10349042

申请日：2003-01-23

申请人： Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

发明人： Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L2701

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A semiconductor structure includes a fin and a layer formed on the fin. The fin includes a first crystalline material having a rectangular cross section and a number of surfaces. The layer is formed on the surfaces and includes a second crystalline material. The first crystalline material has a different lattice constant than the second crystalline material to induce tensile strain within the first layer.

摘要翻译： 半导体结构包括翅片和形成在翅片上的层。 翅片包括具有矩形横截面和多个表面的第一结晶材料。 该层形成在表面上并且包括第二结晶材料。 第一结晶材料具有与第二结晶材料不同的晶格常数，以在第一层内引起拉伸应变。

公开(公告)号：US06765227B1

公开(公告)日：2004-07-20

申请号：US10116791

申请日：2002-04-04

申请人： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

发明人： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

IPC分类号： H01L2906

CPC分类号： H01L29/66742 ,  H01L21/76256 ,  H01L29/1054 ,  H01L29/78687 ,  Y10S438/977

摘要： A semiconductor-on-insulator (SOI) wafer. The wafer includes a silicon substrate, a buried oxide (BOX) layer disposed on the substrate, and an active layer disposed on the box layer. The active layer has an upper silicon layer disposed on a silicon-germanium layer. The silicon-germanium layer is disposed on a lower silicon layer. The silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 Å to about 400 Å thick.

摘要翻译： 绝缘体上半导体（SOI）晶片。 晶片包括硅衬底，设置在衬底上的掩埋氧化物（BOX）层和设置在盒层上的有源层。 有源层具有设置在硅 - 锗层上的上硅层。 硅 - 锗层设置在下硅层上。 硅 - 锗层的硅 - 锗是应变的硅 - 锗，并且是大约至大约400埃。

公开(公告)号：US06716686B1

公开(公告)日：2004-04-06

申请号：US10613997

申请日：2003-07-08

申请人： Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

发明人： Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

IPC分类号： H01L2100

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.

摘要翻译： 用于形成一个或多个FinFET器件的方法包括在氧化物层中形成源极区域和漏极区域，其中氧化物层设置在衬底上，并且蚀刻源极区域和漏极区域之间的氧化物层以形成基团 的第一装置的氧化物壁和通道。 该方法还包括在第一器件的氧化物壁和通道上沉积连接器材料，形成用于第一器件的栅极掩模，从通道移除连接器材料，将沟道材料沉积在第一器件的通道中，形成栅极 在沟道上的第一器件的电介质，在第一器件的栅极电介质上沉积栅极材料，以及图案化和蚀刻栅极材料以形成用于第一器件的至少一个栅电极。

公开(公告)号：US06445016B1

公开(公告)日：2002-09-03

申请号：US09795159

申请日：2001-02-28

申请人： Judy Xilin An ,  Bin Yu

发明人： Judy Xilin An ,  Bin Yu

IPC分类号： H01L31072

CPC分类号： H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

摘要： A silicon-on-insulator (SOI) transistor. The SOI transistor having a source and a drain having a body disposed therebetween, the source being implanted with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hetero junction along a lower portion of the source/body junction.

摘要翻译： 绝缘体上硅（SOI）晶体管。 具有源极和漏极的SOI晶体管具有设置在其间的主体，源被注入锗以形成邻近源极的下部的源极/主体结的硅 - 锗的区域，硅 - 锗的面积 源沿着源极/主体结的下部形成异质结。

公开(公告)号：US06410371B1

公开(公告)日：2002-06-25

申请号：US09794884

申请日：2001-02-26

申请人： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

发明人： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

IPC分类号： H01L2184

CPC分类号： H01L29/66742 ,  H01L21/76256 ,  H01L29/1054 ,  H01L29/78687 ,  Y10S438/977

摘要： A method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a silicon substrate, the substrate of the second wafer having a silicon-germanium layer disposed thereon, a silicon layer disposed on the silicon-germanium layer and an oxide layer disposed on the silicon layer; wafer bonding the first and second wafers; and removing an undesired portion of the substrate from the second wafer to form an upper silicon layer. The resulting SOI wafer structure is also disclosed.

摘要翻译： 一种形成绝缘体上半导体（SOI）晶片的方法。 该方法包括提供第一晶片，第一晶片具有硅衬底和设置在其上的氧化物层的步骤; 提供第二晶片，所述第二晶片具有硅衬底，所述第二晶片的衬底具有设置在其上的硅 - 锗层，设置在所述硅 - 锗层上的硅层和设置在所述硅层上的氧化物层; 晶片接合第一和第二晶片; 以及从所述第二晶片去除所述衬底的不希望的部分以形成上硅层。 还公开了所得到的SOI晶片结构。

公开(公告)号：US06187642B1

公开(公告)日：2001-02-13

申请号：US09334119

申请日：1999-06-15

申请人： Bin Yu ,  Judy Xilin An

发明人： Bin Yu ,  Judy Xilin An

IPC分类号： H01L21336

CPC分类号： H01L29/7834 ,  B01J2219/00315 ,  B01J2219/00317 ,  B01J2219/00527 ,  B01J2219/00585 ,  B01J2219/0059 ,  B01J2219/00596 ,  B01J2219/00605 ,  B01J2219/00653 ,  B01J2219/00659 ,  B01J2219/00686 ,  B01J2219/00689 ,  B01J2219/00713 ,  B01J2219/0072 ,  B01J2219/00722 ,  B01J2219/00725 ,  B01J2219/00731 ,  B82Y5/00 ,  B82Y10/00 ,  C07B2200/11 ,  C07H21/00 ,  C40B40/06 ,  C40B40/10 ,  C40B40/12 ,  C40B60/14 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/04 ,  G11C19/00 ,  H01L25/50 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

摘要： The inventive method provides improved semiconductor devices, such as MOSFET's with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate. The inventive method provides thin first dielectric spacers on the side of a gate and gate oxide and extend from the top of the gate to the surface of the substrate. Raised source/drain extensions are placed on the surface of a substrate, which extend from the first dielectric spacers to the isolation trenches. Thicker second dielectric spacers are placed adjacent to the first dielectric spacers and extend from the top of the first dielectric spacers to the raised source/drain extensions. Raised source/drain regions are placed on the raised source/drain extensions, and extend from the isolation trenches to the second dielectric spacers. The inventive semiconductor devices provide for very shallow source drain extensions which results in a reduced short channel effect.

摘要翻译： 本发明的方法提供了改进的半导体器件，例如在衬底上具有升高的源极/漏极延伸的MOSFET，其中隔离沟槽蚀刻到衬底的表面中。 本发明的方法在栅极和栅极氧化物的一侧提供薄的第一介电间隔物，并且从栅极的顶部延伸到衬底的表面。 引出的源极/漏极延伸部被放置在从第一电介质间隔物延伸到隔离沟槽的衬底的表面上。 更厚的第二电介质间隔物被放置成与第一电介质间隔物相邻并且从第一介电间隔物的顶部延伸到升高的源极/漏极延伸部分。 升高的源极/漏极区域放置在凸起的源极/漏极延伸部上，并且从隔离沟槽延伸到第二电介质间隔物。 本发明的半导体器件提供非常浅的源极漏极延伸，这导致短沟道效应的降低。

公开(公告)号：US07781810B1

公开(公告)日：2010-08-24

申请号：US11538217

申请日：2006-10-03

申请人： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

发明人： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L29/72

CPC分类号： H01L29/7855 ,  H01L21/823821 ,  H01L29/42384 ,  H01L29/7843 ,  H01L29/78684

摘要： A device includes a fin, a first gate and a second gate. The first gate is formed adjacent a first side of the fin and includes a first layer of material having a first thickness and having an upper surface that is substantially co-planar with an upper surface of the fin. The second gate is formed adjacent a second side of the fin opposite the first side and includes a second layer of material having a second thickness and having an upper surface that is substantially co-planar with the upper surface of the fin, where the first thickness and the second thickness are substantially equal to a height of the fin.

摘要翻译： 一种装置包括鳍片，第一栅极和第二栅极。 第一门形成在鳍片的第一侧附近，并且包括具有第一厚度并且具有与鳍片的上表面基本共面的上表面的第一材料层。 所述第二浇口邻近所述翅片的与所述第一侧相对的第二侧形成，并且包括具有第二厚度并具有与所述翅片的上表面基本共面的上表面的第二材料层，其中所述第一厚度 并且第二厚度基本上等于翅片的高度。

公开(公告)号：US06833588B2

公开(公告)日：2004-12-21

申请号：US10274867

申请日：2002-10-22

申请人： Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

发明人： Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

IPC分类号： H01L2701

CPC分类号： H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66803

摘要： A double-gate semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the gate is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin are surrounded by the gate. The gate material surrounding the fin has a U-shaped cross-section at a channel region of the semiconductor device.