公开(公告)号：US08798200B2

公开(公告)日：2014-08-05

申请号：US13202929

申请日：2009-07-03

Applicant: Jin Xu ,  Jun Xu ,  Zhifeng Yuan ,  Qianzi Xu ,  Xianwei Gong ,  Bo Sun ,  Huiying Fang

Inventor： Jin Xu ,  Jun Xu ,  Zhifeng Yuan ,  Qianzi Xu ,  Xianwei Gong ,  Bo Sun ,  Huiying Fang

IPC: H04L27/36 ,  H04L1/00 ,  H04L27/34 ,  H04L1/18

CPC classification number: H04L27/3405 ,  H04L1/0066 ,  H04L1/0071 ,  H04L1/1893

Abstract: The present invention provides a constellation mapping method, and the method includes: flipping a plurality of bits in each modulation symbol unit to be mapped in part of or all of modulation symbol units to be mapped of a bit sequence to be mapped; and mapping each flipped modulation symbol unit to be mapped as a modulation symbol in a constellation. By means of the present invention, the phenomenon that consecutive bits have the same reliability can be effectively avoided by changing unevenness of reliability distribution of the consecutive bits, and at the same time, the link performance can be improved.

Abstract translation: 本发明提供一种星座映射方法，该方法包括：在要映射的比特序列映射的调制符号单元的一部分或全部中，对每个调制符号单元中的多个比特进行翻转， 并映射要映射成星座图中的调制符号的每个翻转的调制符号单元。 通过本发明，可以通过改变连续位的可靠性分布的不均匀性来有效地避免连续位具有相同可靠性的现象，同时可提高链路性能。

公开(公告)号：US08798185B2

公开(公告)日：2014-08-05

申请号：US13577789

申请日：2010-10-22

Applicant: Yijian Chen ,  Wu Yin ,  Yu Ngok Li ,  Jun Xu ,  Xun Yang

Inventor： Yijian Chen ,  Wu Yin ,  Yu Ngok Li ,  Jun Xu ,  Xun Yang

IPC: H04B7/02 ,  H04B7/06 ,  H04L1/00

CPC classification number: H04L1/0025 ,  H04B7/063 ,  H04B7/0645 ,  H04L25/03898

Abstract: The present invention discloses a method for Multiple Input Multiple Output (MIMO) channel information feedback, and the method includes: a terminal selecting part of column vectors for MIMO system feedback from a codebook matrix W corresponding to a Precoding Matrix Indicator (PMI) and marking the selected part of column vectors as Wpart; the terminal determining information O which represents high-precision vector quantification information of MIMO along with the part of column vectors Wpart according to a common representation relationship F, and feeding back the information O to a base station. The present invention also discloses a terminal and a base station which support MIMO. The present invention achieves high-precision and low-overhead channel information feedback and can well support multiple vector feedback needed by high rank (more layer multiplexing) MIMO transmission and high-precision feedback needed by low rank MIMO transmission simultaneously.

Abstract translation: 本发明公开了一种多输入多输出（MIMO）信道信息反馈的方法，该方法包括：从对应于预编码矩阵指示符（PMI）的码本矩阵W中选择一部分用于MIMO系统反馈的列向量， 所选的部分列向量为Wpart; 终端确定信息O，其表示MIMO的高精度矢量量化信息以及根据公共表示关系F的列向量Wpart的一部分，并将信息O反馈到基站。 本发明还公开了一种支持MIMO的终端和基站。 本发明实现了高精度和低开销的信道信息反馈，并且可以很好地支持高秩（多层复用）MIMO传输和低秩MIMO传输所需的高精度反馈所需的多向量反馈。

公开(公告)号：US08785938B2

公开(公告)日：2014-07-22

申请号：US13583851

申请日：2012-08-02

Applicant: Lianfeng Zhao ,  Renrong Liang ,  Mei Zhao ,  Jing Wang ,  Jun Xu

Inventor： Lianfeng Zhao ,  Renrong Liang ,  Mei Zhao ,  Jing Wang ,  Jun Xu

IPC: H01L29/786 ,  H01L29/04

CPC classification number: H01L29/78675 ,  H01L27/1281 ,  H01L29/04 ,  H01L29/66757

Abstract: A method for forming a polycrystalline film, a polycrystalline film formed by the method and a thin film transistor fabricated from the polycrystalline film are provided. The method comprises the steps of: providing a substrate; forming a thermal conductor layer on the substrate; etching the thermal conductor layer until the substrate is exposed to form a thermal conductor pattern; forming a seed layer on the thermal conductor layer and the substrate; etching the seed layer to form seed crystals on both sidewalls of the thermal conductor; forming an amorphous layer on the substrate, the thermal conductor layer and the seed crystals; etching the amorphous layer; and recrystallizing the amorphous layer to form a polycrystalline layer.

Abstract translation: 提供一种形成多晶膜的方法，通过该方法形成的多晶膜和由多晶膜制造的薄膜晶体管。 该方法包括以下步骤：提供衬底; 在所述基板上形成热导体层; 蚀刻热导体层，直到基板被暴露以形成热导体图案; 在导热体层和基板上形成晶种层; 蚀刻种子层以在热导体的两个侧壁上形成晶种; 在基板上形成非晶层，热导体层和晶种; 蚀刻非晶层; 并使非晶层重结晶以形成多晶层。

公开(公告)号：US20140145314A1

公开(公告)日：2014-05-29

申请号：US13816164

申请日：2012-12-18

Applicant: JING Wang ,  Renrong Liang ,  Lei Guo ,  Jun Xu

Inventor： JING Wang ,  Renrong Liang ,  Lei Guo ,  Jun Xu

IPC: H01L29/04

CPC classification number: H01L29/04 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/0276 ,  H01L21/28255 ,  H01L21/823807 ,  H01L29/06 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/24 ,  H01L29/517 ,  H01L29/78

Abstract: A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of beryllium oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is single crystal beryllium oxide.

Abstract translation: 提供了具有氧化铍的半导体结构。 半导体结构包括：半导体衬底（100）; 以及交替层叠在半导体基板（100）上的多个绝缘氧化物层（201,202,20.0x）和多个单晶半导体层（301,302,30 ...）。 与半导体衬底（100）接触的绝缘氧化物层（201）的材料是氧化铍，SiO 2，SiO x N y及其组合中的任一种，其它绝缘氧化物层（202.20x）的材料是单晶 氧化铍。

公开(公告)号：US20140054546A1

公开(公告)日：2014-02-27

申请号：US13703722

申请日：2012-10-18

Applicant: Libin Liu ,  Renrong Liang ,  Jing Wang ,  Jun Xu

Inventor： Libin Liu ,  Renrong Liang ,  Jing Wang ,  Jun Xu

IPC: H01L29/775 ,  H01L29/78 ,  H01L29/66 ,  H01L27/108

CPC classification number: H01L29/775 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785

Abstract: A dynamic random access memory unit and a method for fabricating the same are provided. The dynamic random access memory unit comprises: a substrate; an insulating buried layer formed on the substrate; a body region formed on the insulating buried layer and used as a charge storing region; two isolation regions formed on the body region, in which a semiconductor contact region is formed between the isolation regions and is a charge channel; a source, a drain and a channel region formed on the isolation regions and the semiconductor contact region respectively and constituting a transistor operating region which is partially separated from the charge storing region by the isolation regions and connected with the charge storing region via the charge channel; a gate dielectric layer formed on the transistor operating region, a gate formed on the gate dielectric layer; a source metal contact layer, a drain metal contact layer.

Abstract translation: 提供了动态随机存取存储单元及其制造方法。 动态随机存取存储器单元包括：衬底; 形成在基板上的绝缘掩埋层; 形成在绝缘掩埋层上并用作电荷存储区域的体区; 形成在体区的两个隔离区，其中在隔离区之间形成半导体接触区，并且是电荷通道; 分别形成在所述隔离区域和所述半导体接触区域上的源极，漏极和沟道区域，并且构成晶体管工作区域，所述晶体管工作区域由所述隔离区域部分地与所述电荷存储区域分离，并且经由所述充电沟道与所述电荷存储区域连接 ; 形成在所述晶体管工作区上的栅介质层，形成在所述栅介质层上的栅极; 源极金属接触层，漏极金属接触层。

公开(公告)号：US08642414B2

公开(公告)日：2014-02-04

申请号：US13132768

申请日：2011-01-19

Applicant: Jing Wang ,  Lei Guo ,  Jun Xu

Inventor： Jing Wang ,  Lei Guo ,  Jun Xu

IPC: H01L21/336

CPC classification number: H01L29/1054 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A MOS transistor structure with an in-situ doped source and/or drain and a method for forming the same are provided. The method comprises steps of: providing a substrate; forming a high Ge content layer on the substrate; forming a gate stack on the high Ge content layer and forming a side wall of one or more layers on both sides of the gate stack; etching the high Ge content layer to form a source region and/or a drain region; and forming a source and/or a drain in the source region and/or the drain region respectively by a low-temperature selective epitaxy, and introducing a doping gas during the low-temperature selective epitaxy to heavily dope the source and/or the drain and to in-situ activate a doping element.

Abstract translation: 提供具有原位掺杂源极和/或漏极的MOS晶体管结构及其形成方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成高Ge含量层; 在高Ge含量层上形成栅极叠层，并在栅叠层的两侧形成一层或多层的侧壁; 蚀刻高Ge含量层以形成源区和/或漏区; 以及通过低温选择性外延分别在源区和/或漏区中形成源极和/或漏极，并且在低温选择性外延期间引入掺杂气体以使源极和/或漏极 并原位激活掺杂元素。

公开(公告)号：US20140024410A1

公开(公告)日：2014-01-23

申请号：US13552753

申请日：2012-07-19

Applicant: Fei HE ,  Jun Xu ,  Lizhong Zhu

Inventor： Fei HE ,  Jun Xu ,  Lizhong Zhu

IPC: H04W88/06 ,  H04W52/52

CPC classification number: H04W52/36 ,  H04W88/06

Abstract: A mobile wireless communications device may include a housing, a cellular transceiver carried by the housing and to operate at a given transmit power level from among different transmit power levels, and a WLAN transceiver carried by the housing and to operate at a given receive gain level from among different receive gain levels. The mobile wireless communications device may also include a controller to select the given receive gain level based upon the given transmit power level of the cellular transceiver.

Abstract translation: 移动无线通信设备可以包括外壳，由外壳承载的蜂窝收发器，并且在不同发射功率电平之间的给定发射功率电平下操作，以及由外壳承载并在给定的接收增益级别 从不同的接收增益水平。 移动无线通信设备还可以包括控制器，用于基于蜂窝收发器的给定发射功率电平来选择给定的接收增益电平。

公开(公告)号：US08635513B1

公开(公告)日：2014-01-21

申请号：US13363898

申请日：2012-02-01

Applicant: Siu-Hung Fred Au ,  Gregory Burd ,  Zining Wu ,  Jun Xu ,  Ichiro Kikuchi ,  Tony Yoon

Inventor： Siu-Hung Fred Au ,  Gregory Burd ,  Zining Wu ,  Jun Xu ,  Ichiro Kikuchi ,  Tony Yoon

IPC: H03M13/00

CPC classification number: H03M13/458 ,  H03M13/098 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/153 ,  H03M13/1545 ,  H03M13/1555 ,  H03M13/2906 ,  H03M13/3707 ,  H03M13/4146 ,  H03M13/45 ,  H03M13/451 ,  H03M13/63 ,  H03M13/6511

Abstract: Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

Abstract translation: 提供了用于在里德 - 所罗门（RS）纠错系统中实现列表解码的系统和方法。 检测器可以从信道提供判决码字，并且还可以为判决码字提供软信息。 软信息可以被组织成用于列表解码的错误事件的组合的顺序。 RS解码器可以使用使用流水线列表解码器架构的列表解码器。 列表解码器可以包括可以并行计算综合征的一个或多个综合征修改电路。 长分割电路可以包括并行地计算多个商多项式系数的多个单元。 列表解码器可以采用迭代解码和有效性测试来产生错误指示符。 迭代解码和有效性测试可以使用较低的综合征。

公开(公告)号：US08607125B2

公开(公告)日：2013-12-10

申请号：US11795826

申请日：2005-05-13

Applicant: Jun Xu ,  Liuqing Yuan ,  Liujun Hu

Inventor： Jun Xu ,  Liuqing Yuan ,  Liujun Hu

IPC: H03M13/00

CPC classification number: H03M13/033 ,  H03M13/1105 ,  H03M13/1148 ,  H03M13/118

Abstract: The codec includes an encoding/decoding operation module and a basic matrix storage module. In the stored basic matrix Hb, for all girths with length of 4, any column element of i, j, k or l constituting the girths in anti-clockwise or clockwise always satisfies inequality: (i−j+k−1) mod z≠0, wherein z is the extension factor. When generating the basic matrix, firstly the number of rows M, number of columns N, and weight vectors of the rows and columns are determined, an irregularly original basic matrix is constructed; then the position of ‘1’ is filled by a value chosen from set {0, 1, 2, . . . , z−1} to obtain the basic matrix Hb. The basic matrix Hb obtained by storing constitutes the desired encoder/decoder. The encoder/decoder according to the present invention can effectively eliminate error-floor phenomenon of LDPC codes and accelerate the falling speed of BER curve.

Abstract translation: 编解码器包括编码/解码操作模块和基本矩阵存储模块。 在存储的基本矩阵Hb中，对于长度为4的所有周长，构成反时针或顺时针的周长的i，j，k或l的任何列元素总是满足不等式：（i-j + k-1）mod z <> 0，其中z是扩展因子。 当生成基本矩阵时，首先确定行数M，列数N和行和列的加权向量，构建不规则原始基本矩阵; 那么'1'的位置由从{{0，1，2，...}中选择的值填充。 。 。 ，z-1}以获得基本矩阵Hb。 通过存储获得的基本矩阵Hb构成所需的编码器/解码器。 根据本发明的编码器/解码器可以有效地消除LDPC码的错误现象，加快BER曲线的下降速度。

公开(公告)号：US08592864B2

公开(公告)日：2013-11-26

申请号：US13499661

申请日：2011-06-27

Applicant: Jing Wang ,  Jun Xu ,  Lei Guo

Inventor： Jing Wang ,  Jun Xu ,  Lei Guo

IPC: H01L21/02

CPC classification number: H01L29/267 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device comprises: a substrate (1); an insulating layer (2), formed on the substrate (1) and having a trench (21) to expose an upper surface of the substrate (1); a first buffer layer (3), formed on the substrate (1) and in the trench (21); and a compound semiconductor layer (4), formed on the first buffer layer (3), wherein an aspect ratio of the trench (21) is larger than 1 and smaller than 10, wherein the first buffer layer (3) is formed by a low-temperature reduced pressure chemical vapor deposition process at a temperature between 200° C. and 500° C., and wherein the compound semiconductor layer (4) is formed by a low-temperature metal organic chemical vapor deposition process at a temperature between 200° C. and 600° C.

Abstract translation: 提供半导体器件及其形成方法。 半导体器件包括：衬底（1）; 形成在所述基板（1）上并具有用于露出所述基板（1）的上表面的沟槽（21）的绝缘层（2）; 形成在所述基板（1）和所述沟槽（21）中的第一缓冲层（3）; 和形成在第一缓冲层（3）上的化合物半导体层（4），其中沟槽（21）的纵横比大于1且小于10，其中第一缓冲层（3）由 在200℃至500℃之间的温度下进行低温减压化学气相沉积工艺，其中化合物半导体层（4）通过低温金属有机化学气相沉积工艺在200℃ ℃和600℃