公开(公告)号：US5600163A

公开(公告)日：1997-02-04

申请号：US291752

申请日：1994-08-16

Applicant: Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L21/8247 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/04 ,  G11C16/28 ,  H01L21/28 ,  H01L21/336 ,  H01L27/01 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/036 ,  H01L31/062 ,  H01L31/112 ,  H01L31/113

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/7888 ,  G11C2216/06 ,  G11C2216/08 ,  H01L27/1203 ,  H01L29/785

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Abstract translation: 一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。 栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。 通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

公开(公告)号：US08093723B2

公开(公告)日：2012-01-10

申请号：US13098648

申请日：2011-05-02

Applicant: Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

Inventor： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract translation: 在具有多层埋地布线的半导体集成电路器件中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US07411301B2

公开(公告)日：2008-08-12

申请号：US11239371

申请日：2005-09-30

Applicant: Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

Inventor： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract translation: 在具有多层埋地布线的半导体集成电路器件中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US20080061298A1

公开(公告)日：2008-03-13

申请号：US11931369

申请日：2007-10-31

Applicant: Kazuo YANO ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo YANO ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L29/04 ,  H01L29/78

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

Abstract: A semiconductor memory device includes a plurality of memory cells, each including, a source region formed of a semiconductor material, a drain region formed of the semiconductor material, and a first region formed of the semiconductor material and located between the source region and the drain region. First and second insulator films sandwich the first region and a first gate electrode is connected to the first region through the first insulator film. In this arrangement, the first region is adapted to accumulate charges corresponding to stored information.

Abstract translation: 半导体存储器件包括多个存储器单元，每个存储单元包括由半导体材料形成的源极区域，由半导体材料形成的漏极区域和由半导体材料形成并位于源极区域和漏极之间的第一区域 地区。 第一和第二绝缘膜夹着第一区域，第一栅电极通过第一绝缘膜连接到第一区域。 在这种布置中，第一区域适于累积对应于存储的信息的费用。

公开(公告)号：US20060208315A1

公开(公告)日：2006-09-21

申请号：US11439152

申请日：2006-05-24

Applicant: Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L29/76

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

公开(公告)号：US07023091B2

公开(公告)日：2006-04-04

申请号：US10465541

申请日：2003-06-20

Applicant: Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni

Inventor： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract translation: 在具有多层埋地布线的半导体集成电路器件中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US20060027928A1

公开(公告)日：2006-02-09

申请号：US11239371

申请日：2005-09-30

Applicant: Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni

Inventor： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni

IPC: H01L23/52

CPC classification number: H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

公开(公告)号：US06674117B2

公开(公告)日：2004-01-06

申请号：US09915588

申请日：2001-07-27

Applicant: Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L2976

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

公开(公告)号：US06643193B2

公开(公告)日：2003-11-04

申请号：US10247301

申请日：2002-09-20

Applicant: Takashi Yamaki ,  Kan Takeuchi ,  Mitsuru Hirakii ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masamichi Fujito

Inventor： Takashi Yamaki ,  Kan Takeuchi ,  Mitsuru Hirakii ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masamichi Fujito

IPC: G11C700

CPC classification number: G11C29/50008 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/28 ,  G11C16/30 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.

公开(公告)号：US06291852B1

公开(公告)日：2001-09-18

申请号：US09521970

申请日：2000-03-09

Applicant: Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L2976

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

Abstract: A field-effect semiconductor element implemented with a reduced number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature. In accordance with one embodiment, a carrier confinement region, isolated from a channel and a gate of the semiconductor FET element, is provided to operate as a storage node for trapping the carrier or carriers.

Abstract translation: 一种场效应半导体元件，其具有减少的元件数量和减少的面积，并且能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。 栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。 通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。 根据一个实施例，提供了从沟道隔离的载流子限制区域和半导体FET元件的栅极，以用作捕获载体或载流子的存储节点。