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公开(公告)号：US07459743B2
公开(公告)日：2008-12-02
申请号：US11161962
申请日：2005-08-24
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。
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公开(公告)号：US07439568B2
公开(公告)日：2008-10-21
申请号：US10906238
申请日：2005-02-10
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译： 提供了垂直场效应晶体管（“FET”），其包括晶体管本体区域和设置在与沟槽的侧壁相邻的衬底的绝缘体上的单晶半导体（“SOI”）区域中的源极和漏极区域。 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。
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公开(公告)号：US07264982B2
公开(公告)日：2007-09-04
申请号：US10904255
申请日：2004-11-01
IPC分类号： H01L21/027
CPC分类号： H01L31/105 , H01L31/03529 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： Trench type PIN photodetectors are formed by etching two sets of trenches simultaneously in a semiconductor substrate, the wide trenches having a width more than twice as great as the narrow trenches by a process margin; conformally filling both types of trenches with a sacrificial material doped with a first dopant and having a first thickness slightly greater than one half the width of the narrow trenches, so that the wide trenches have a remaining central aperture; stripping the sacrificial material from the wide trenches in an etch that removes a first thickness, thereby emptying the wide trenches; a) filling the wide trenches with a second sacrificial material of opposite polarity; or b) doping the wide trenches from the ambient such as by gas phase doping, plasma doping, ion implantation, liquid phase doping, infusion doping and plasma immersion ion implantation; diffusing the dopants into the substrate, forming p and n regions of the PIN diode; removing the first and the second sacrificial materials, and filling both the wide and the narrow sets of trenches with the same conductive material in contact with the diffused p and n regions.
摘要翻译： 通过在半导体衬底中同时蚀刻两组沟槽形成沟槽型PIN光电检测器，宽沟槽的宽度是窄沟槽的两倍以上的加工余量; 用掺杂有第一掺杂剂的牺牲材料保形地填充两种类型的沟槽，并且具有略大于窄沟槽宽度的一半的第一厚度，使得宽沟槽具有剩余的中心孔径; 在去除第一厚度的蚀刻中从宽的沟槽剥离牺牲材料，从而排空宽的沟槽; a）用相反极性的第二牺牲材料填充宽的沟槽; 或b）通过气相掺杂，等离子体掺杂，离子注入，液相掺杂，浸渍掺杂和等离子体浸入离子注入等方式，从环境中掺杂宽沟槽; 将掺杂剂扩散到衬底中，形成PIN二极管的p区和n区; 去除第一和第二牺牲材料，并用与扩散的p和n区域接触的相同导电材料填充宽和窄的沟槽组。
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公开(公告)号：US07060546B2
公开(公告)日：2006-06-13
申请号：US10707200
申请日：2003-11-26
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3205 , H01L21/4763 , H01L21/44
CPC分类号： H01L29/66772 , H01L21/76283 , H01L29/458 , H01L29/66545
摘要： An ultra-thin, scaleable MOSFET transistor and fabrication method are described. The transistor features fully self-aligned, raised source/drain junctions on a thin SOI wafer and exhibits low contact resistance, low gate resistance and good device isolation characteristic. No extra lithographic mask steps are required beyond those required by conventional processes. The transistor is completely “bracketed” or surrounded by STI (shallow trench isolation), providing inherent isolation between it and any other devices on the SOI wafer. Gate sidewall spacers are formed outside of the gate area so that the scalability is limited solely by lithography resolution.
摘要翻译： 描述了一种超薄的可扩展MOSFET晶体管和制造方法。 晶体管在薄SOI晶圆上具有完全自对准的升高的源极/漏极结，并且具有低接触电阻，低栅极电阻和良好的器件隔离特性。 不需要额外的光刻掩模步骤，超出传统工艺所需要的步骤。 晶体管完全“包围”或被STI（浅沟槽隔离）包围，提供了SOI晶片上任何其他器件之间的固有隔离。 栅极侧壁间隔物形成在栅极区域的外部，从而可扩展性仅由光刻分辨率限制。
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25.发明授权Structure and process for compact cell area in a stacked capacitor cell array 失效叠层电容器阵列中紧凑单元面积的结构和工艺公开(公告)号：US06455886B1
公开(公告)日：2002-09-24
申请号：US09636564
申请日：2000-08-10
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L29/66181
摘要： A method for forming, and a structure for a semiconductor device having vertically-oriented transistors connected to stacked capacitor cells, wherein a contact area for the capacitors enables a compact cell. A vertically-oriented transistor is formed in a trough in a substrate above a buried bit line. The gate conductor may be formed in the trough above the buried bit line, with source and drain diffusions spaced along a sidewall of the trough. Isolation regions are formed in the semiconductor substrate to isolate the transistors. Word lines are formed above the surface of the semiconductor substrate in a direction perpendicular to the direction of the buried bit lines. A capacitor contact is formed above the surface of the semiconductor substrate at a contact area of an active region between adjacent word lines. The active region is rhomboid in shape, enabling a low capacitor contact resistance, a small bit line and word line pitch, and consequently, a compact capacitor cell.
摘要翻译： 一种用于形成的方法，以及具有连接到层叠电容器单元的垂直取向的晶体管的半导体器件的结构，其中电容器的接触面积使得能够实现紧凑的电池。 垂直取向的晶体管形成在掩埋位线上方的衬底的槽中。 栅极导体可以形成在掩埋位线上方的槽中，源极和漏极扩散沿着槽的侧壁间隔开。 在半导体衬底中形成隔离区以隔离晶体管。 在与掩埋位线的方向垂直的方向上在半导体衬底的表面上形成字线。 在相邻字线之间的有源区域的接触区域处，在半导体衬底的表面上方形成电容器触点。 有源区域是菱形形状，能够实现低电容器接触电阻，小位线和字线间距，从而实现紧凑的电容器单元。
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公开(公告)号：US06440872B1
公开(公告)日：2002-08-27
申请号：US09706468
申请日：2000-11-03
IPC分类号： H01L2100
CPC分类号： H01L27/10867 , H01L27/10876
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.
摘要翻译： 形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。
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公开(公告)号：US06414347B1
公开(公告)日：2002-07-02
申请号：US09790011
申请日：2001-02-09
IPC分类号： H01L2972
CPC分类号： H01L27/10864 , H01L21/2255 , H01L21/26586 , H01L27/10841 , H01L29/66666 , H01L29/7827
摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.
摘要翻译： 一种用于制造垂直MOSFET结构的改进方法，包括：一种形成半导体存储单元阵列结构的方法，包括：提供垂直MOSFET DRAM单元结构，其具有平坦化到覆盖硅上的沟槽顶部氧化物的顶表面的沉积栅极导体层 基质; 在所述硅衬底的顶表面下方的所述栅极导体层中形成凹部; 以一定角度注入N型掺杂剂物质通过凹槽形成阵列P-阱中的掺杂凹坑; 将氧化物层沉积到所述凹部中并蚀刻所述氧化物层以在所述凹部的侧壁上形成间隔物; 将栅极导体材料沉积到所述凹部中并将所述栅极导体平坦化到所述沟槽顶部氧化物的所述顶表面。
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28.发明授权Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays 有权在EDRAM阵列中形成双功能高性能支持MOSFET的方法公开(公告)号：US06261894B1
公开(公告)日：2001-07-17
申请号：US09706492
申请日：2000-11-03
IPC分类号： H01L218234
CPC分类号： H01L27/10864 , H01L27/10894 , H01L27/10897
摘要： Methods of preparing dual workfunction high-performance support metal oxide semiconductor field effect transistor (MOSFETs)/embedded dynamic random access (EDRAM) arrays are provided. The methods describe herein reduce the number of deep-UV masks used in the forming memory structure, decouple the support and arraying processing steps, provide salicided gates, source/drain regions and bitlines, and provide, in some instances, local interconnects at no additional processing costs. Dual workfunction high-performance support MOSFETs/ EDRAM arrays having a gate conductor guard ring and/or local interconnections are also provided.
摘要翻译： 提供双功能功能高性能支持金属氧化物半导体场效应晶体管（MOSFET）/嵌入式动态随机存取（EDRAM）阵列的方法。 这里描述的方法减少了在形成存储器结构中使用的深UV掩模的数量，解耦支持和排列处理步骤，提供盐化栅极，源极/漏极区域和位线，并且在一些情况下提供局部互连， 加工成本。 还提供了双功能功能的高性能支持具有栅极导体保护环和/或局部互连的MOSFET / EDRAM阵列。
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29.发明授权Simplified vertical array device DRAM/eDRAM integration: method and structure 有权简化垂直阵列器件DRAM / eDRAM集成：方法和结构公开(公告)号：US07485910B2
公开(公告)日：2009-02-03
申请号：US10907630
申请日：2005-04-08
IPC分类号： H01L27/108
CPC分类号： H01L27/12 , H01L27/10841 , H01L27/10891
摘要： The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active area by a pad nitride. The present invention also provides methods that are capable of forming the inventive semiconductor structure.
摘要翻译： 本发明提供一种半导体结构，其包括位于半导体存储器件上方的有源字线和位于所述有源字线附近并位于衬底的有效区域之上的被动字线。 根据本发明，被动字线通过衬垫氮化物与有源区分离。 本发明还提供了能够形成本发明的半导体结构的方法。
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公开(公告)号：US07009237B2
公开(公告)日：2006-03-07
申请号：US10709450
申请日：2004-05-06
申请人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
发明人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.
摘要翻译： 本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件 掩埋氧化层。 上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。 上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。 垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。
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