公开(公告)号：US20130009192A1

公开(公告)日：2013-01-10

申请号：US13368043

申请日：2012-02-07

申请人： Hyun Wook Shim ,  Dong Ju Lee ,  Dong Ik Shin ,  Young Sun Kim ,  Makoto Asai ,  Yu Ri Sohn

发明人： Hyun Wook Shim ,  Dong Ju Lee ,  Dong Ik Shin ,  Young Sun Kim ,  Makoto Asai ,  Yu Ri Sohn

IPC分类号： H01L33/30

CPC分类号： H01L33/025 ,  H01L29/452 ,  H01L33/32 ,  H01L33/40

摘要： Provided is a nitride semiconductor light emitting device including p-type nitride semiconductor layer, an n-type nitride semiconductor layer, and an active layer formed therebetween. A contact layer is positioned between the p-type nitride semiconductor layer and a p-side electrode. The contact layer includes a first p-type nitride layer having a first impurity concentration to form ohmic contact with the p-side electrode and a second p-type nitride layer having a second impurity concentration, the second impurity concentration having a concentration lower than the first impurity concentration.

摘要翻译： 提供了包括p型氮化物半导体层，n型氮化物半导体层和在它们之间形成的有源层的氮化物半导体发光器件。 接触层位于p型氮化物半导体层和p侧电极之间。 接触层包括具有第一杂质浓度以与p侧电极欧姆接触的第一p型氮化物层和具有第二杂质浓度的第二p型氮化物层，第二杂质浓度的浓度低于 第一杂质浓度。

公开(公告)号：US07977704B2

公开(公告)日：2011-07-12

申请号：US12320497

申请日：2009-01-27

申请人： Masaki Koyama ,  Yoshifumi Okabe ,  Makoto Asai ,  Takeshi Fujii ,  Koh Yoshikawa

发明人： Masaki Koyama ,  Yoshifumi Okabe ,  Makoto Asai ,  Takeshi Fujii ,  Koh Yoshikawa

IPC分类号： H01L29/739

CPC分类号： H01L29/7395 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/7397

摘要： A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

摘要翻译： 具有IGBT的半导体器件包括：基板; 衬底上的漂移层和基底层; 穿过基层的沟槽将基层分成基部; 一个基部的发射极区域; 沟槽中的栅极元件; 发射极; 和集电极。 一个基座部分提供通道层，而另一个基座部件提供没有发射极区域的浮动层。 栅极元件包括靠近沟道层的栅极电极和与浮置层相邻的伪栅极电极。 浮子层包括与沟道层相邻的第一浮动层和与沟道层分开的第二浮体层。 虚拟栅电极和第一浮动层与基层上的第一浮动布线耦合。 虚拟栅电极与第二浮动层隔离。

公开(公告)号：US20110012195A1

公开(公告)日：2011-01-20

申请号：US12865330

申请日：2009-01-28

申请人： Seiji Momota ,  Hitoshi Abe ,  Takashi Shiigi ,  Takeshi Fujii ,  Koh Yoshikawa ,  Tetsutaro Imagawa ,  Masaki Koyama ,  Makoto Asai

发明人： Seiji Momota ,  Hitoshi Abe ,  Takashi Shiigi ,  Takeshi Fujii ,  Koh Yoshikawa ,  Tetsutaro Imagawa ,  Masaki Koyama ,  Makoto Asai

IPC分类号： H01L27/11

CPC分类号： H01L27/0629 ,  H01L27/0658 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7815 ,  H01L29/7827

摘要： Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).

摘要翻译： 在主装置（24）的源电极（25）和电流检测装置（21）的电流检测电极（22）之间连接用于检测电流的电阻器。 栅极绝缘体（36）的介电耐受电压大于电阻器和流过电流检测装置（21）的反向偏压的最大电流的乘积。 主装置（24）的p体区域（32）的扩散长度短于电流检测装置（21）的p体（31）的扩散长度。 主装置（24）的p体区域（32）的端部的曲率半径比电流检测装置（21）的p体（31）的曲率半径小。 结果，在逆偏压下，主装置（24）的p体区域（32）的端部的电场变得比电流检测装置的p体区域（31）的电场强 21）。 因此，主装置24中的雪崩击穿比电流检测装置（21）更容易发生。

公开(公告)号：US07838396B2

公开(公告)日：2010-11-23

申请号：US11594898

申请日：2006-11-09

申请人： Yumi Maruyama ,  Makoto Asai

发明人： Yumi Maruyama ,  Makoto Asai

IPC分类号： H01L21/00

CPC分类号： H01L21/67132 ,  B23K26/40 ,  B23K26/53 ,  B23K2103/50 ,  B28D5/0011 ,  B28D5/0052 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/12 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/13099 ,  H01L2224/29 ,  H01L2224/29007 ,  H01L2224/29298 ,  H01L2224/32014 ,  H01L2224/83101 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/15787 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： A semiconductor substrate is bonded to a joining face of a sheet and is dividable along predetermined dividing lines of the semiconductor substrate by expanding the sheet so as to form semiconductor chips. A bonding layer for bonding a substrate face of the semiconductor substrate and the joining face of the sheet to each other can be formed in each region encircled with the predetermined dividing lines, between the substrate face and the joining face of the sheet. Thus, when the substrate face of the semiconductor substrate and the joining face of the sheet are bonded to each other, the bonding layer does not reach any of the predetermined dividing lines set between the regions. The bonding layer can be formed in dotted segments or a pattern of lattice between the substrate face of the semiconductor substrate and the joining face of the sheet.

摘要翻译： 半导体基板被接合到片材的接合面，并且可以通过使片材膨胀从而沿着半导体衬底的预定划分线分割以形成半导体芯片。 用于将半导体衬底的衬底表面和片材的接合面彼此接合的接合层可以在衬底表面和片材的接合面之间的每个区域中形成有围绕预定划分线的每个区域。 因此，当半导体基板的基板面和薄板的接合面彼此接合时，接合层不会到达设置在这些区域之间的任何预定划分线。 接合层可以以虚线部分或半导体衬底的衬底面与片的接合面之间的格子图案形成。

公开(公告)号：US20090283798A1

公开(公告)日：2009-11-19

申请号：US12213469

申请日：2008-06-19

申请人： Yukio Tsuzuki ,  Makoto Asai

发明人： Yukio Tsuzuki ,  Makoto Asai

IPC分类号： H01L29/739 ,  H01L27/06 ,  H01L21/8232 ,  H01L21/331

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7806

摘要： A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.

摘要翻译： 半导体器件包括具有主侧和后侧的n导电型半导体衬底，布置在衬底的主侧上的p导电型层，布置在p导电型中的主侧n导电型区域 层，布置在基板的后侧上的后侧n导电型层，到达基板并穿透主侧n导电型区域和p导电型层的第一沟槽，到达基板的第二沟槽 在p导电型层的内部，嵌入在第二沟槽中并连接到p导电型层的第二电极层。 因此，可以获得其中二极管电池的恢复特性可以在不损害MOS晶体管单元或IGBT单元的性能而不损坏浪涌耐受性的情况下得到的半导体器件。

公开(公告)号：US20070120205A1

公开(公告)日：2007-05-31

申请号：US11649254

申请日：2007-01-04

申请人： Minoru Murata ,  Kenichi Yokoyama ,  Makoto Asai

发明人： Minoru Murata ,  Kenichi Yokoyama ,  Makoto Asai

IPC分类号： G01P15/08

CPC分类号： G01C19/5719 ,  G01P15/125

摘要： A semiconductor physical quantity sensor includes: a substrate; a semiconductor layer supported on the substrate; a trench disposed in the semiconductor layer; and a movable portion disposed in the semiconductor layer and separated from the substrate by the trench. The movable portion includes a plurality of through-holes, each of which penetrates the semiconductor layer in a thickness direction. The movable portion is capable of displacing on the basis of a physical quantity applied to the movable portion so that the physical quantity is detected by a displacement of the movable portion. The movable portion has a junction disposed among the through-holes. The junction has a trifurcate shape.

摘要翻译： 半导体物理量传感器包括：基板; 支撑在基板上的半导体层; 设置在所述半导体层中的沟槽; 以及可移动部分，其设置在所述半导体层中并且通过所述沟槽与所述衬底分离。 可动部包括在厚度方向上贯穿半导体层的多个贯通孔。 可移动部分能够基于施加到可移动部分的物理量来移位，使得通过可移动部分的位移来检测物理量。 可动部分具有设置在通孔中的接合部。 交界处有三叉形。

公开(公告)号：US06452214B2

公开(公告)日：2002-09-17

申请号：US09523463

申请日：2000-03-10

申请人： Naoki Kaneyama ,  Makoto Asai ,  Katsuhisa Sawazaki

发明人： Naoki Kaneyama ,  Makoto Asai ,  Katsuhisa Sawazaki

IPC分类号： H01L3300

CPC分类号： H01L33/32 ,  B82Y20/00 ,  H01S5/0421 ,  H01S5/34333

摘要： A cap layer of GaN about 140 Å thick and a p-type clad layer of Mg-doped p-type AlxGa1−xN (x=0.12) about 200 Å thick are formed successively on an MQW active layer about 230 Å thick. A p-type contact layer of Mg-doped p-type AlyGa1−yN (y=0.05) about 600 Å thick is further formed thereon. These composition ratios x and y are selected to satisfy the expression “0.03≦0.3x≦y≦0.5x≦0.08”, so that the composition of the p-type contact layer becomes close to the composition of the p-type clad layer.

摘要翻译： 在大约大的厚度的MQW有源层上依次形成厚度大约为140埃的覆盖层和约200埃的Mg掺杂的p型Al x Ga 1-x N（x = 0.12）的p型覆盖层。 在其上进一步形成约600埃厚的Mg掺杂的p型Al y Ga 1-y N（y = 0.05）的p型接触层。 选择这些组成比x和y以满足表达式“0.03 <= 0.3×<= y <= 0.5×<= 0.08”，使得p型接触层的组成变得接近p- 型覆层。

公开(公告)号：US4732731A

公开(公告)日：1988-03-22

申请号：US900429

申请日：1986-08-26

申请人： Makoto Asai ,  Shoji Shiga ,  Toru Tanigawa ,  Yoshimasa Oyama ,  Shigeo Shinozaki

发明人： Makoto Asai ,  Shoji Shiga ,  Toru Tanigawa ,  Yoshimasa Oyama ,  Shigeo Shinozaki

IPC分类号： H01L23/48 ,  C22C9/00 ,  C22C9/02 ,  C22C9/06 ,  C22F1/08 ,  H01L23/495

CPC分类号： H01L23/49579 ,  C22C9/02 ,  C22C9/06 ,  C22F1/08 ,  H01L2924/0002

摘要： A copper alloy is disclosed, which contains 0.1 to 3.0 wt % of Ni, 0.1 to 1.0 wt % of Ti, the ratio of Ni to Ti being 4.ltoreq.Ni/Ti thereby, 0.1 to 6.0 wt % of Sn, and 0.005 to 3.0 wt % in total of one or more elements selected from the group consisting of Zn, Mn, Mg, Ca, RE, B, Sb, Te, Si, Co, Fe, Zr, Ag, Mm and Al, and consists of the remainder of Cu and the inevitable impurities. The method for the manufacture of the alloy is characterized in that, after copper alloy ingot was maintained and homogenized for 0.5 to 15 hours at 750.degree. to 960.degree. C. prior to rolling, the hot rolling is carried out starting from a temperature of 700.degree. to 880.degree. C. and the cooling is made immediately after the end of rolling.

摘要翻译： 公开了一种铜合金，其含有0.1〜3.0重量％的Ni，0.1〜1.0重量％的Ti，Ni与Ti的比例为4≤Ni/ Ti，0.1〜6.0重量％的Sn和0.005 至少3.0重量％的选自Zn，Mn，Mg，Ca，RE，B，Sb，Te，Si，Co，Fe，Zr，Ag，Mm和Al中的一种或多种元素，并且由 剩余的Cu和不可避免的杂质。 合金的制造方法的特征在于，在轧制之后，在750〜960℃保持铜合金锭并均化0.5〜15小时后，从700℃的温度开始进行热轧 DEG至880℃，并在轧制结束后立即进行冷却。

公开(公告)号：US08097901B2

公开(公告)日：2012-01-17

申请号：US13115137

申请日：2011-05-25

申请人： Masaki Koyama ,  Yoshifumi Okabe ,  Makoto Asai ,  Takeshi Fujii ,  Koh Yoshikawa

发明人： Masaki Koyama ,  Yoshifumi Okabe ,  Makoto Asai ,  Takeshi Fujii ,  Koh Yoshikawa

IPC分类号： H01L29/739

CPC分类号： H01L29/7395 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/7397

摘要： A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

摘要翻译： 具有IGBT的半导体器件包括：基板; 衬底上的漂移层和基底层; 穿过基层的沟槽将基层分成基部; 一个基部的发射极区域; 沟槽中的栅极元件; 发射极; 和集电极。 一个基座部分提供通道层，而另一个基座部件提供没有发射极区域的浮动层。 栅极元件包括靠近沟道层的栅极电极和与浮置层相邻的伪栅极电极。 浮子层包括与沟道层相邻的第一浮动层和与沟道层分开的第二浮体层。 虚拟栅电极和第一浮动层与基层上的第一浮动布线耦合。 虚拟栅电极与第二浮动层隔离。

公开(公告)号：US07838331B2

公开(公告)日：2010-11-23

申请号：US11598654

申请日：2006-11-14

申请人： Atsushi Komura ,  Tetsuo Fujii ,  Muneo Tamura ,  Makoto Asai

发明人： Atsushi Komura ,  Tetsuo Fujii ,  Muneo Tamura ,  Makoto Asai

IPC分类号： H01L21/00

CPC分类号： H01L21/67132 ,  B23K26/009 ,  B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50 ,  B28D5/0011 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3192 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： A device separated from a wafer includes: a chip having a sidewall, which is provided by a dicing surface of the wafer in a case where the device is separated from the wafer; and a protection member disposed on the sidewall of the chip for protecting the chip from being contaminated by a dust from the dicing surface. In the device, the dicing surface of the wafer is covered with the protection member so that the chip is prevented from contaminated with the dust.

摘要翻译： 与晶片分离的器件包括：具有侧壁的芯片，其在器件与晶片分离的情况下由晶片的切割表面提供; 以及设置在芯片的侧壁上的保护构件，用于保护芯片免受来自切割表面的灰尘的污染。 在该装置中，晶片的切割面被保护部件覆盖，从而防止芯片被灰尘污染。