公开(公告)号：US08578135B2

公开(公告)日：2013-11-05

申请号：US13423145

申请日：2012-03-16

申请人： Teppei Hirotsu ,  Yuuichi Abe ,  Takeshi Kataoka ,  Yasuhiro Nakatsuka

发明人： Teppei Hirotsu ,  Yuuichi Abe ,  Takeshi Kataoka ,  Yasuhiro Nakatsuka

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/30054 ,  G06F9/3804 ,  G06F9/382

摘要： A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.

摘要翻译： 能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。 它是配备有CPU，存储器，预取装置等的信息处理装置，其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支 从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址，从而期待分支目的地址。 信息处理装置还包括RTS指令缓冲器，用于存储RTS指令的返回目的地的一系列指令，存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。

公开(公告)号：US08423661B2

公开(公告)日：2013-04-16

申请号：US12873893

申请日：2010-09-01

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Kei Ouchi ,  Yoshihiro Tanaka ,  Toshinobu Kanai ,  Masanobu Tanaka ,  Kenji Furuhashi ,  Tomoaki Aoki

IPC分类号： G06F13/00

CPC分类号： H04L47/6255 ,  H04L12/44 ,  H04L47/10 ,  H04L47/2458 ,  H04L47/30 ,  H04L47/522 ,  H04L49/205 ,  H04L49/3018 ,  H04L49/351

摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.

公开(公告)号：US20080177855A1

公开(公告)日：2008-07-24

申请号：US12076686

申请日：2008-03-21

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Yasuwo Watanabe

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Yasuwo Watanabe

IPC分类号： G06F15/16

CPC分类号： H04L69/16 ,  H04L49/90 ,  H04L69/161 ,  H04L69/162 ,  H04L69/22

摘要： A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits and receives a packet between the controlled object and the network terminal, further includes a copy and operation unit that is a hardware unit for executing the checksum calculation to check for a packet error and the copy operation. The copy and operation unit performs the packet data copy operation and the checksum calculation simultaneously between a sending buffer/receiving buffer, formed in the memory and used by the packet communication circuit, and a work area used by a communication processing program, thus reducing the load of the CPU and increasing the communication processing speed.

摘要翻译： 包括CPU，存储器和分组通信电路的分组通信装置充当远程监视和控制受控对象的网络连接受控对象和网络终端之间的接口，并且在 受控对象和网络终端还包括作为用于执行校验和计算以检查分组错误和复制操作的硬件单元的复制和操作单元。 复制和操作单元在存储器中形成并由分组通信电路使用的发送缓冲器/接收缓冲器与由通信处理程序使用的工作区域之间同时执行分组数据复制操作和校验和计算，从而减少 加载CPU并增加通信处理速度。

公开(公告)号：US07142213B2

公开(公告)日：2006-11-28

申请号：US10822672

申请日：2004-04-13

申请人： Yasuhiro Nakatsuka ,  Keisuke Nakashima ,  Shigeru Matsuo ,  Masahisa Narita ,  Koyo Katsura ,  Hidehito Takewa ,  Tomoaki Aoki

发明人： Yasuhiro Nakatsuka ,  Keisuke Nakashima ,  Shigeru Matsuo ,  Masahisa Narita ,  Koyo Katsura ,  Hidehito Takewa ,  Tomoaki Aoki

IPC分类号： G06F15/00 ,  G06T1/20 ,  G09G5/36

CPC分类号： G06T15/40 ,  G06T1/20

摘要： In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

摘要翻译： 在执行图像数据的处理（显示和输出）的装置和系统中，保持图像数据的存储器和处理图像数据的处理器之间传送的数据量受到限制，从而可以在高处处理大量的数据 速度。

公开(公告)号：US20060202992A1

公开(公告)日：2006-09-14

申请号：US11432350

申请日：2006-05-12

申请人： Yasuhiro Nakatsuka ,  Shigeru Matsuo ,  Jun Satoh ,  Masanori Miyoshi ,  Koyo Katsura ,  Takashi Sone

发明人： Yasuhiro Nakatsuka ,  Shigeru Matsuo ,  Jun Satoh ,  Masanori Miyoshi ,  Koyo Katsura ,  Takashi Sone

IPC分类号： G06T15/50 ,  G06T15/60

CPC分类号： G06T1/60 ,  G06T11/40 ,  G06T15/50 ,  G06T15/80

摘要： In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.

公开(公告)号：US06717583B2

公开(公告)日：2004-04-06

申请号：US09991705

申请日：2001-11-26

申请人： Tetsuya Shimomura ,  Shigeru Matsuo ,  Koyo Katsura ,  Tatsuki Inuzuka ,  Yasuhiro Nakatsuka

发明人： Tetsuya Shimomura ,  Shigeru Matsuo ,  Koyo Katsura ,  Tatsuki Inuzuka ,  Yasuhiro Nakatsuka

IPC分类号： G06F15167

CPC分类号： G09G5/001 ,  G06F13/1673 ,  G06F13/18 ,  G09G5/02 ,  G09G5/363 ,  G09G5/393 ,  G09G5/395 ,  G09G2340/02 ,  G09G2360/121 ,  G09G2360/125 ,  G09G2360/128

摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.

摘要翻译： 为了减少由于使用主存储器的一部分作为显示帧缓冲器而导致的数据处理器的处理性能的劣化，当从CPU 310产生对存储器200的访问请求时，存储器控制器400保持 一旦请求显示控制器560停止对正在执行的存储器200的访问，当已经从存储器200传送已经执行的访问的数据时，显示控制器560保持它，并且从被保持的CPU总线310传送访问请求 当CPU总线310的访问结束时，存储器控制器400重新启动在显示控制器560中停止的访问，并将保持的数据传送到显示控制器560。

公开(公告)号：US6167497A

公开(公告)日：2000-12-26

申请号：US871978

申请日：1997-06-10

申请人： Yasuhiro Nakatsuka ,  Koyo Katsura

发明人： Yasuhiro Nakatsuka ,  Koyo Katsura

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F9/30138

摘要： A data processing apparatus includes physical registers larger in number than logical registers specified by a register specification field of an instruction executed by the apparatus. The physical registers are classified into a plurality of banks. In response to a particular instruction, an execution control section supplies a register address converter with bank information to select a bank of the physical register. The converter stores the bank information in a bank register. Receiving logical register address information specified by the register specification field of the instruction, the address converter adds the bank information set to the bank register to at least a portion of the logical register address information, thereby producing a physical register address which can specify any one of the physical registers.

摘要翻译： 数据处理装置包括数量大于由装置执行的指令的寄存器指定字段指定的逻辑寄存器的物理寄存器。 物理寄存器分为多个存储体。 响应于特定指令，执行控制部分向寄存器地址转换器提供银行信息以选择一个物理寄存器组。 转换器将银行信息存储在银行寄存器中。 接收由指令的寄存器指定字段指定的逻辑寄存器地址信息，地址转换器将存储体信息设置添加到存储体寄存器至少部分逻辑寄存器地址信息，从而产生一个物理寄存器地址， 的物理寄存器。

公开(公告)号：US5748202A

公开(公告)日：1998-05-05

申请号：US498055

申请日：1995-07-05

申请人： Yasuhiro Nakatsuka ,  Keisuke Nakashima ,  Shigeru Matsuo ,  Masahisa Narita ,  Koyo Katsura ,  Hidehito Takewa ,  Tomoaki Aoki

发明人： Yasuhiro Nakatsuka ,  Keisuke Nakashima ,  Shigeru Matsuo ,  Masahisa Narita ,  Koyo Katsura ,  Hidehito Takewa ,  Tomoaki Aoki

IPC分类号： G06T3/00 ,  G06T1/20 ,  G06T15/40 ,  G06F12/00

CPC分类号： G06T15/40 ,  G06T1/20

摘要： In a device and system which perform processing, (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

摘要翻译： 在执行图像数据的处理（显示和输出）的装置和系统中，保持图像数据的存储器和处理图像数据的处理器之间传送的数据量受到限制，从而可以处理大量数据 高速。

公开(公告)号：US07557809B2

公开(公告)日：2009-07-07

申请号：US10983757

申请日：2004-11-09

申请人： Yasuhiro Nakatsuka ,  Tetsuya Shimomura ,  Manabu Jyou ,  Yuichiro Morita ,  Takashi Hotta ,  Kazushige Yamagishi ,  Yutaka Okada

发明人： Yasuhiro Nakatsuka ,  Tetsuya Shimomura ,  Manabu Jyou ,  Yuichiro Morita ,  Takashi Hotta ,  Kazushige Yamagishi ,  Yutaka Okada

IPC分类号： G06F13/14 ,  G09G5/39 ,  G06F15/167

CPC分类号： G09G5/39 ,  G09G2360/125

摘要： The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

摘要翻译： 多媒体数据处理系统的基本部分包括CPU 1100，图像显示单元2100，统一存储器1200，系统总线1920和连接到系统总线的设备1300,1400和1500。 在这种配置中，CPU形成在安装在包括指令处理单元1110和显示控制单元1140的单个硅晶片上的LSI上。主存储区域1210和显示区域1220存储在统一存储器内。 与用于连接LSI和输入/输出设备的系统总线无关地提供用于连接对应的LSI和统一存储器的统一存储器端口1910。 统一的存储器端口可以比系统总线更快地驱动。

公开(公告)号：US07496679B2

公开(公告)日：2009-02-24

申请号：US10446929

申请日：2003-05-29

申请人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Yoshihiro Tanaka ,  Kenji Furuhashi

发明人： Hiroshi Arita ,  Yasuhiro Nakatsuka ,  Yasuwo Watanabe ,  Yoshihiro Tanaka ,  Kenji Furuhashi

IPC分类号： G06F15/16

CPC分类号： H04L29/06 ,  H04L49/90 ,  H04L69/08

摘要： A packet communication apparatus capable of performing packet conversion at high speed for packet transfer or packet transmission/reception has: a packet conversion unit for performing packet conversion for a reception packet received at a plurality of communication units and for a transmission packet to be transmitted from the plurality of communication units; and a transfer control unit for outputting, when the reception packet received by the communication unit is judged as a the transfer packet, the reception packet to a transfer buffer, for outputting the transmission packet to the communication unit corresponding to the communication object at a destination of the transmission packet generated by a packet generating and processing unit, and for outputting the transfer packet to the communication unit corresponding to the communication object at a destination of the transfer packet stored in the transfer buffer.

摘要翻译： 能够高速进行分组转换以进行分组传送或分组发送/接收的分组通信装置具有：分组转换单元，用于对在多个通信单元接收的接收分组进行分组转换，以及对于要从 所述多个通信单元; 以及传送控制单元，用于当将由通信单元接收到的接收分组判断为传送分组时，将接收分组输出到传送缓冲器，用于将发送分组输出到与目的地的通信对象相对应的通信单元 由分组产生和处理单元产生的传输分组，并且用于将存储在传送缓冲器中的传送分组的目的地处的传送分组输出到与通信对象对应的通信单元。