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30 条记录 (耗时 0.029 秒)

    Information processing equipment capable of multicolor display
    21.
    发明授权
    Information processing equipment capable of multicolor display 失效
    能够进行多色显示的信息处理设备

    公开(公告)号：US5390293A

    公开(公告)日：1995-02-14

    申请号：US107181

    申请日：1993-08-17

    申请人： Kiyokazu Nishioka ,  Hideki Kamimaki ,  Tsutomu Furuhashi ,  Kohji Takahashi ,  Bunichi Fujimaki ,  Koichi Isaji

    发明人： Kiyokazu Nishioka ,  Hideki Kamimaki ,  Tsutomu Furuhashi ,  Kohji Takahashi ,  Bunichi Fujimaki ,  Koichi Isaji

    IPC分类号： G06F1/32 ,  G09G3/20 ,  G09G3/36 ,  G09G5/02 ,  G06F15/00

    CPC分类号： G09G3/20 ,  G06F1/3218 ,  G09G3/2003 ,  G09G2310/08 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2340/0428 ,  G09G3/2018 ,  G09G3/3607 ,  G09G5/026

    摘要： An information processing equipment capable of multicolor display, comprising a CPU; a display memory which stores display information therein; a display unit which displays the display information in multiple colors selected from a predetermined number of colors to-be-developed; a display control circuit which controls transfer of information between the CPU and the display memory, and which regularly reads out the display information stored in the display memory and then sends the read-out display information to the display unit; a mode selector which selects one of at least two modes consisting of a first mode and a second mode, and which produces selection information, wherein the first mode causes the display unit to develop a smaller number of multiple colors and to operate at a lower frequency, while the second mode causes the display unit to develop a large number of multiple colors and to operate at a higher frequency; a clock signal generator which generates a plurality of clock signals of unequal frequencies; a clock selector circuit which receives the selection information to select the clock signal of the frequency corresponding to the mode indicated by the selection information, from among the plurality of clock signals delivered from the clock signal generator, and which delivers the selected clock signal to, at least, the display control circuit; and a maximum-number-of-colors selector which is provided in, for example, the display unit, and which receives the selection information to control the number of colors to-be-developed that are to be displayed by the display unit, to the number corresponding to the mode indicated by the selection information.

    摘要翻译： 一种能够进行多色显示的信息处理设备，包括CPU; 存储其中的显示信息的显示存储器; 显示单元，其显示从要开发的预定颜色的颜色中选择的多种颜色的显示信息; 显示控制电路，其控制CPU和显示存储器之间的信息传送，并且定期读出存储在显示存储器中的显示信息，然后将读出的显示信息发送到显示单元; 模式选择器，其选择由第一模式和第二模式组成的至少两种模式中的一种，并且产生选择信息，其中第一模式使显示单元产生较少数量的多种颜色并以较低频率操作 而第二模式使得显示单元产生大量多种颜色并以更高的频率工作; 时钟信号发生器，其产生不等频的多个时钟信号; 时钟选择器电路，从时钟信号发生器传送的多个时钟信号中接收选择信息以选择与由选择信息指示的模式相对应的频率的时钟信号，并将选择的时钟信号传送到， 至少显示控制电路; 以及设置在例如显示单元中的最大数量的颜色选择器，并且其接收选择信息以控制要由显示单元显示的待显示的颜色的数量，以及 对应于由选择信息指示的模式的号码。

    VLIW system with predicated instruction execution for individual instruction fields
    24.
    发明授权
    VLIW system with predicated instruction execution for individual instruction fields 失效
    具有针对各个指令字段执行预定指令的VLIW系统

    公开(公告)号：US6041399A

    公开(公告)日：2000-03-21

    申请号：US884667

    申请日：1997-06-27

    申请人： Koichi Terada ,  Keiji Kojima ,  Yoshifumi Fujikawa ,  Tohru Nojiri ,  Kiyokazu Nishioka

    发明人： Koichi Terada ,  Keiji Kojima ,  Yoshifumi Fujikawa ,  Tohru Nojiri ,  Kiyokazu Nishioka

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/34 ,  G06F9/38 ,  G06F9/45

    CPC分类号： G06F9/3885 ,  G06F9/30072 ,  G06F9/3824

    摘要： In the case of constituting a processing unit having the characteristic of a VLIW type processing unit and the characteristic of a pipeline type processing unit, since reference to the result of operations is made among a plurality of processing units executing in parallel the operations, transfer of the register file is frequently generated among the processing units, resulting in insufficient effect of the high speed operations. In view of solving this problem, the predicate registers are provided and moreover a means for broadcasting the update data of the predicate register to all processing units is also provided. Thereby, operations for obtaining branching condition and numerical value can be realized in different processing units and the number of steps of the processing program can be reduced. In addition, since high speed transfer between the processing units of the data register having a wider bit width is no longer required and thereby the mounting area can be reduced and high speed processing unit can be realized.

    摘要翻译： 在构成具有VLIW类型处理单元的特征的处理单元和流水线类型处理单元的特性的情况下，由于在并行执行操作的多个处理单元中进行操作结果的参考，因此， 在处理单元之间经常生成寄存器文件，导致高速操作的效果不足。 为了解决这个问题，提供了谓词寄存器，并且还提供了用于向所有处理单元广播谓词寄存器的更新数据的装置。 因此，可以在不同的处理单元中实现获得分支条件和数值的操作，并且可以减少处理程序的步数。 此外，由于不再需要具有较宽位宽的数据寄存器的处理单元之间的高速传输，从而可以减小安装面积，并可实现高速处理单元。

    Processor and data processor
    25.
    发明授权
    Processor and data processor 失效
    处理器和数据处理器

    公开(公告)号：US5870618A

    公开(公告)日：1999-02-09

    申请号：US681180

    申请日：1996-07-22

    申请人： Yoshifumi Fujikawa ,  Keiji Kojima ,  Kiyokazu Nishioka ,  Tohru Nojiri ,  Kazuhiko Tanaka ,  Masao Ishiguro

    发明人： Yoshifumi Fujikawa ,  Keiji Kojima ,  Kiyokazu Nishioka ,  Tohru Nojiri ,  Kazuhiko Tanaka ,  Masao Ishiguro

    IPC分类号： G06F9/305 ,  G06F9/30 ,  G06F9/302 ,  G06F9/34 ,  G06F9/38 ,  G06F9/26

    CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/30101

    摘要： An object of the present invention is to provide a processor which can execute calculation between data of a data length larger than the data length of the register file at high speed without the cost of the hardware being increased so much and the first long register 12 and the second long register 13 having a bit width which is two times of the bit width of the register file and the long register update device 14 for updating the data of the second long register 13 partially are installed between the register file 2 and the pixel calculator 11. When the long register update pixel calculation instruction is stored in the instruction register 31, the long register update device 14 connects a part of the data of the second long register 13 and a part of data read from the register file 2 and sends them to the pixel calculator 11 and the second long register 13 via the selector 15. The pixel calculator 11 executes calculation between the data of the first long register 12 and the data given from the selector 15.

    摘要翻译： 本发明的目的是提供一种处理器，其可以在高速的数据长度大于寄存器文件的数据长度的数据长度的数据之间进行计算，而不会增加硬件的成本，并且第一长寄存器12和 具有位宽度为寄存器堆的位宽度的二倍的第二长寄存器13和用于更新第二长寄存器13的数据的长寄存器更新装置14部分地安装在寄存器堆2和像素计算器 当长寄存器更新像素计算指令存储在指令寄存器31中时，长寄存器更新装置14连接第二长寄存器13的数据的一部分和从寄存器文件2读取的数据的一部分，并将它们发送 经由选择器15传送到像素计算器11和第二长寄存器13.像素计算器11执行第一长寄存器12的数据和数据gi之间的计算 从选择器15发出。

    Pipeline processor including interrupt control system for accurately perform interrupt processing even applied to VLIW and delay branch instruction in delay slot
    26.
    发明授权
    Pipeline processor including interrupt control system for accurately perform interrupt processing even applied to VLIW and delay branch instruction in delay slot 失效
    管道处理器包括中断控制系统，用于准确执行中断处理，甚至应用于VLIW，并延迟延迟槽中的分支指令

    公开(公告)号：US5815696A

    公开(公告)日：1998-09-29

    申请号：US888789

    申请日：1997-07-07

    申请人： Kazuhiko Tanaka ,  Tohru Nojiri ,  Keiji Kojima ,  Kiyokazu Nishioka ,  Yoshiki Kurokawa

    发明人： Kazuhiko Tanaka ,  Tohru Nojiri ,  Keiji Kojima ,  Kiyokazu Nishioka ,  Yoshiki Kurokawa

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48

    CPC分类号： G06F9/327 ,  G06F9/30149 ,  G06F9/3804

    摘要： There is provided an instruction supply unit 20 for generating addresses for each instruction when an interrupt occurs, from an interrupted instruction until an instruction to be executed later by the number of instructions contained in a delay slot of the instruction an interrupt control unit 50 for storing each address thus generated, and an instruction executing unit 30 for successively reading out each of the stored addresses from the address of the interrupted address after the interrupt processing is completed. The instruction executing unit 30 executes a branch instruction to the address which is first read out. Thereafter, with respect to the addresses which are read out secondly and subsequently, if the address is the branch destination address of the branch instruction, the instruction executing unit 30 executes the branch instruction to the address, and if the address is not the branch destination address, it executes an NOP instruction. Accordingly, even when the instruction length is not fixed, the interrupt can be accurately processed.

    摘要翻译： 提供了一个指令提供单元20，用于当中断发生时，从中断指令到稍后执行的指令的指令生成指令的延迟时隙中的指令数量，用于存储每个指令的地址，中断控制单元50用于存储 每个地址如此生成，以及指令执行单元30，用于在完成中断处理之后，从中断地址的地址中连续地读出每个存储的地址。 指令执行单元30对首先被读出的地址执行分支指令。 此后，对于第二次读出的地址，随后，如果地址是分支指令的分支目的地地址，则指令执行单元30对该地址执行分支指令，如果地址不是分支目的地 地址，它执行一个NOP指令。 因此，即使指令长度不固定，也能够正确地进行中断处理。

    Logic LSI
    27.
    发明授权
    Logic LSI 失效
    逻辑LSI

    公开(公告)号：US5585750A

    公开(公告)日：1996-12-17

    申请号：US478403

    申请日：1995-06-07

    申请人： Kouki Noguchi ,  Kiyokazu Nishioka ,  Shinya Ohba ,  Susumu Narita

    发明人： Kouki Noguchi ,  Kiyokazu Nishioka ,  Shinya Ohba ,  Susumu Narita

    IPC分类号： G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G06F1/32 ,  H01L21/82

    CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3287 ,  Y02B60/1217 ,  Y02B60/1282

    摘要： A logic LSI has a plurality of modules such as a CPU contained in one chip. Frequency changing conditions, signals for designating modules whose frequencies are changed for each frequency changing condition, and signals for designating frequencies to be changed are stored in a storage device of a frequency controller, software-wise. The sequentially-input status of the logic LSI is compared with the stored frequency changing conditions and, when the former conforms to the latter, a signal for changing the corresponding frequency is applied to each of the plurality of modules. Each of the modules generates a plurality of internal clocks in synchronization with the basic clock and selects one out of the internal clocks according to the frequency changing signal.

    摘要翻译： 逻辑LSI具有包含在一个芯片中的诸如CPU的多个模块。 频率变化条件，用于为每个频率变化条件改变频率的指定模块的信号和用于指定要改变的频率的信号被存储在频率控制器的存储装置中。 将逻辑LSI的顺序输入状态与存储的频率变化条件进行比较，并且当前者符合后者时，将用于改变相应频率的信号应用于多个模块中的每一个。 每个模块与基本时钟同步地产生多个内部时钟，并根据频率变化信号选择一个内部时钟。

    Information processor having high speed and safety resume system
    28.
    发明授权
    Information processor having high speed and safety resume system 失效
    具有高速和安全恢复系统的信息处理器

    公开(公告)号：US5485623A

    公开(公告)日：1996-01-16

    申请号：US205708

    申请日：1994-03-03

    申请人： Yoshiki Kurokawa ,  Kiyokazu Nishioka ,  Hideki Kamimaki ,  Yoshifumi Atarashi

    发明人： Yoshiki Kurokawa ,  Kiyokazu Nishioka ,  Hideki Kamimaki ,  Yoshifumi Atarashi

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/3287 ,  G06F1/3203 ,  Y02B60/1282

    摘要： An information processor operating with a battery writes data which exists in a register of a CPU at that time into a predetermined stack area for transfer of an RAM when a suspend command is received in the normal operation state of the processor and shifts to the suspended state that the power supply to the minimum circuit components including the RAM is maintained and the power supply to the other circuit components is stopped. When insufficient power of the battery is detected in the suspended state, the information processor is started temporarily so as to automatically transfer and store the data in the RAM into a storage device using a non-volatile memory device.

    摘要翻译： 当处理器的正常运行状态下接收到暂停命令时，利用电池操作的信息处理器将此时存在于CPU的寄存器中的数据写入到用于传送RAM的预定堆栈区域中的数据，并转移到暂停状态 维持包括RAM的最小电路部件的电源，并停止对其他电路部件的供电。 当在暂停状态下检测到电池电量不足时，临时启动信息处理器，以便使用非易失性存储装置将RAM中的数据自动传送和存储到存储装置中。