公开(公告)号：US20080277735A1

公开(公告)日：2008-11-13

申请号：US11800615

申请日：2007-05-07

申请人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Ta-Ming Kuan ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Ta-Ming Kuan ,  Wen-Chin Lee

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.

摘要翻译： 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅电极相邻的深源/漏区; 深源/漏区上的硅化物区; 以及在硅化物区域和栅电极之间的升高的金属化源极/漏极区域。 升高的金属化源极/漏极区域邻接硅化物区域。

公开(公告)号：US20080145984A1

公开(公告)日：2008-06-19

申请号：US11640713

申请日：2006-12-18

申请人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

发明人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843

摘要： A method for forming a semiconductor structure includes: providing a semiconductor substrate; forming an NMOS device at a surface of the semiconductor substrate, which comprises forming a first source/drain electrode on a first source/drain region of the NMOS device, wherein the first source/drain electrode has a first barrier height; forming a PMOS device at the surface of the semiconductor substrate comprising forming a second source/drain electrode on a second source/drain region of the PMOS device, wherein the second source/drain electrode has a second barrier height, and wherein the first barrier height is different from the second barrier height; forming a first stressed film having a first intrinsic stress over the NMOS device; and forming a second stressed film having a second intrinsic stress over the PMOS device, wherein the first intrinsic stress is more tensile than the second intrinsic stress.

摘要翻译： 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底的表面上形成NMOS器件，其包括在所述NMOS器件的第一源极/漏极区域上形成第一源极/漏极，其中所述第一源极/漏极具有第一势垒高度; 在所述半导体衬底的表面上形成PMOS器件，包括在所述PMOS器件的第二源极/漏极区域上形成第二源极/漏极电极，其中所述第二源极/漏极具有第二势垒高度，并且其中所述第一势垒高度 与第二屏障高度不同; 在NMOS器件上形成具有第一固有应力的第一应力膜; 以及在所述PMOS器件上形成具有第二固有应力的第二应力膜，其中所述第一本征应力比所述第二固有应力更具拉伸力。

公开(公告)号：US07355262B2

公开(公告)日：2008-04-08

申请号：US11378907

申请日：2006-03-17

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/76224 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon migration, forming a rounded or a T-shaped surface of the diffusion regions. The method may further include recessing a portion of the diffusion region before performing the DTE. The diffusion region has a slanted surface after performing the DTE.

摘要翻译： 半导体结构使用扩散地形工程（DTE）形成。 优选的方法包括提供半导体衬底，形成限定扩散区域的沟槽隔离区域，在半导体衬底上的含氢环境中进行DTE，以及在扩散区域中形成MOS器件。 DTE导致硅迁移，形成扩散区域的圆形或T形表面。 该方法还可以包括在执行DTE之前使扩散区的一部分凹陷。 在执行DTE之后，扩散区域具有倾斜表面。

公开(公告)号：US20070215936A1

公开(公告)日：2007-09-20

申请号：US11378907

申请日：2006-03-17

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/76224 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon migration, forming a rounded or a T-shaped surface of the diffusion regions. The method may further include recessing a portion of the diffusion region before performing the DTE. The diffusion region has a slanted surface after performing the DTE.

摘要翻译： 半导体结构使用扩散地形工程（DTE）形成。 优选的方法包括提供半导体衬底，形成限定扩散区域的沟槽隔离区域，在半导体衬底上的含氢环境中进行DTE，以及在扩散区域中形成MOS器件。 DTE导致硅迁移，形成扩散区域的圆形或T形表面。 该方法还可以包括在执行DTE之前使扩散区的一部分凹陷。 在执行DTE之后，扩散区域具有倾斜表面。

公开(公告)号：US20100090256A1

公开(公告)日：2010-04-15

申请号：US12249152

申请日：2008-10-10

申请人： Hung-Wei Chen ,  Yider Wu

发明人： Hung-Wei Chen ,  Yider Wu

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/7843 ,  H01L29/7881

摘要： A semiconductor structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zones to yield stress different in level; and a barrier plug separating the two device zones from each other. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and a relatively lower reading voltage is needed to obtain initially required reading current. As a result, the probability of stress-induced leakage current (SILC) is reduced and the semiconductor memory structure may have enhanced data retention ability.

摘要翻译： 具有应力区域的半导体结构包括限定第一和第二器件区的衬底; 形成在所述第一和第二装置区域中的每一个中的第一和第二应力区域，以产生不同水平的应力; 以及将两个装置区彼此分开的阻挡塞。 由于在应力区产生的应力，载流子迁移率增加，因此可以获得增加的读取电流，并且需要相对较低的读取电压来获得最初需要的读取电流。 结果，应力诱发漏电流（SILC）的概率降低，并且半导体存储器结构可能具有增强的数据保留能力。

公开(公告)号：US07538351B2

公开(公告)日：2009-05-26

申请号：US11089405

申请日：2005-03-23

申请人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

发明人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

IPC分类号： H01L29/10

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/7854

摘要： A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of and ; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of and different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.

摘要翻译： 一种半导体器件及其制造方法，包括提供先进半导体器件的改进的静电放电保护，所述半导体器件包括提供具有预选择的表面取向和晶体方向的半导体衬底; 覆盖半导体衬底的绝缘体层; 覆盖绝缘体层的第一半导体有源区具有选自<100>和<110>的第一表面取向; 延伸穿过绝缘体层的厚度部分的第二半导体有源区，其具有选自与第一表面取向不同的<110>和<100>的第二表面取向; 其中包括第一导电类型的第一MOS器件的MOS器件设置在第一半导体有源区上，并且第二导电类型的第二MOS器件设置在第二半导体有源区上。

公开(公告)号：US20070103568A1

公开(公告)日：2007-05-10

申请号：US11415255

申请日：2006-05-02

申请人： Hung-Wei Chen

发明人： Hung-Wei Chen

IPC分类号： H04N5/262

CPC分类号： H04N5/2628

摘要： A method of enlarging an image by interpolation means and a related digital camera are disclosed. The method comprises: dividing an original image into a plurality of divided sections; defining a first divided section selected from the plurality of divided sections; defining a second divided section from the divided sections adjacent thereto and continuing until defining a final divided section; enlarging the first divided section by a first specific multiplier and zooming out by a second specific multiplier by using the interpolation means to form a first processed section, and continuing until a final processed section is formed. The first processed section to the final processed section thereby form an enlarged image.

摘要翻译： 公开了一种通过插值装置和相关数字照相机放大图像的方法。 该方法包括：将原始图像划分成多个划分的部分; 限定从所述多个分割部分中选择的第一分割部分; 从与其相邻的分割部分定义第二分割部分，并且继续直到定义最终分割部分; 通过第一特定乘法器放大第一分割区域并通过使用内插装置来缩放第二特定乘数，以形成第一处理部分，并且继续直到形成最终处理部分。 第一处理部分到最终处理部分，从而形成放大图像。

公开(公告)号：US07074692B2

公开(公告)日：2006-07-11

申请号：US10807081

申请日：2004-03-23

申请人： Hung-Wei Chen ,  Hsun-Chin Tsao ,  Kuang-Hsin Chen ,  Di-Houng Lee

发明人： Hung-Wei Chen ,  Hsun-Chin Tsao ,  Kuang-Hsin Chen ,  Di-Houng Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： Methods of reducing a short channel phenomena for an NMOS device formed in an SOI layer, wherein the short channel phenomena is created by boron movement from a channel region to adjacent insulator regions, has been developed. A first embodiment of this invention entails the formation of a boron or nitrogen doped insulator layer located underlying the NMOS device. This is accomplished via formation of shallow trench openings in composite silicon nitride-silicon shapes, followed by lateral pull back of the silicon nitride shapes exposing portions of the top surface of the silicon shapes, followed by implantation of boron or nitrogen ions into portions of the insulator layer exposed in the STI openings and into portions of the insulator layer underlying exposed portions of the silicon shapes. A subsequent hydrogen anneal procedure finalizes the doped insulator layer which alleviates boron segregation from an overlying NMOS channel region. A second embodiment features the formation of a dielectric barrier layer on the surfaces of STI openings preventing boron from segregated to silicon oxide filled STI regions. A combination of both embodiments can be employed to reduce and prevent boron segregation to both underlying and adjacent insulator regions, thus reducing the risk of short channel phenomena.

摘要翻译： 已经开发了减少在SOI层中形成的NMOS器件的短通道现象的方法，其中通过硼从沟道区域移动到相邻的绝缘体区域产生短沟道现象。 本发明的第一实施例需要形成位于NMOS器件下面的硼或氮掺杂的绝缘体层。 这是通过在复合氮化硅 - 硅形状中形成浅沟槽开口而实现的，随后氮化硅形状的横向拉回暴露出硅形状的顶表面的部分，然后将硼或氮离子注入到 绝缘体层暴露在STI开口中并且沉积在硅形状的暴露部分下面的绝缘体层的部分中。 随后的氢退火程序完成掺杂的绝缘体层，其减轻了从上覆的NMOS沟道区域的硼偏析。 第二实施例的特征在于在STI开口的表面上形成介电阻挡层，防止硼偏析到填充氧化硅的STI区域。 可以采用两种实施方案的组合来减少和防止硼分离到下面的和相邻的绝缘体区域，从而降低短沟道现象的风险。

公开(公告)号：US20060049460A1

公开(公告)日：2006-03-09

申请号：US10989080

申请日：2004-11-15

申请人： Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

发明人： Hung-Wei Chen ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L27/12

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/7842 ,  H01L29/785

摘要： In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

摘要翻译： 在本发明的优选实施例中，描述了使用SOI和混合衬底取向形成CMOS器件的方法。 根据优选实施例，衬底可以具有多个晶体取向。 衬底中的一个逻辑门可以包括在一个晶体取向上的至少一个N-FET和另一个晶体取向上的至少一个P-FET。 衬底中的另一个逻辑门可以包括至少一个N-FET和至少一个相同取向的P-FET。 替代实施例还包括确定基板的优选解理平面并且考虑到它们各自优选的解理平面使基板相对于彼此定向。 在优选实施例中，解理平面不平行。

公开(公告)号：US20050112817A1

公开(公告)日：2005-05-26

申请号：US10916023

申请日：2004-08-11

申请人： Shui-Ming Cheng ,  Hung-Wei Chen ,  Zhong Xuan

发明人： Shui-Ming Cheng ,  Hung-Wei Chen ,  Zhong Xuan

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/76 ,  H01L21/338

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness, and raised source and drain regions disposed on either side of the gate structure. The method further comprises forming a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, where the second semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device, and recessed source and drain regions disposed on either side of the gate structure.

摘要翻译： 一种方法包括在衬底中形成第一半导体器件，其中第一半导体器件包括栅极结构，设置在栅极结构的侧壁上的间隔物，间隔物具有第一厚度，以及升高的源极和漏极区域，其设置在 门结构。 所述方法还包括在所述衬底中形成第二半导体器件并与所述第一半导体器件电隔离，其中所述第二半导体器件包括栅极结构，设置在所述栅极结构的侧壁上的间隔物，所述间隔物的第二厚度小于 第一半导体器件的间隔物的第一厚度，以及设置在栅极结构的任一侧的凹陷的源极和漏极区域。