公开(公告)号：US20120179412A1

公开(公告)日：2012-07-12

申请号：US13423624

申请日：2012-03-19

申请人： Azeez Bhavnagarwala ,  David J. Frank ,  Stephen V. Kosonocky

发明人： Azeez Bhavnagarwala ,  David J. Frank ,  Stephen V. Kosonocky

IPC分类号： G06F19/00

CPC分类号： G11C29/50004 ,  G01R31/2603 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3173 ,  G01R31/31937 ,  G11C11/41 ,  G11C29/50 ,  G11C2029/5002

摘要： Circuits for measuring and characterizing random variations in device characteristics of integrated circuit devices.

摘要翻译： 用于测量和表征集成电路器件器件特性随机变化的电路。

公开(公告)号：US08193799B2

公开(公告)日：2012-06-05

申请号：US12236003

申请日：2008-09-23

申请人： Stephen V. Kosonocky ,  Samuel D. Naffziger ,  Visvesh S. Sathe

发明人： Stephen V. Kosonocky ,  Samuel D. Naffziger ,  Visvesh S. Sathe

IPC分类号： B23K11/24

CPC分类号： H01L25/16 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0262 ,  H05K2201/10378 ,  Y10T307/406 ,  H01L2224/0401

摘要： A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device.

摘要翻译： 公开了一种包括被称为集成电路插入器的电子设备的装置。 集成电路包括电压调节器模块。 插入器附接到诸如另一集成电路的电子设备，并且便于对电子设备的电力的控制和分配。 集成电路插入器还可以在附接的电子设备和另一电子设备之间进行信令。 集成电路插入器上的电压调节器模块可以被配置为向附接的电子设备提供电压参考信号。 根据电子设备的工作要求，可以使能或禁止由集成电路插入器产生电压参考信号，并且可以调节电压参考信号的值。

公开(公告)号：US20110261064A1

公开(公告)日：2011-10-27

申请号：US12766403

申请日：2010-04-23

申请人： Spencer Gold ,  Stephen V. Kosonocky ,  Samuel Naffziger

发明人： Spencer Gold ,  Stephen V. Kosonocky ,  Samuel Naffziger

IPC分类号： G09G5/39 ,  G06F12/00

CPC分类号： G11C11/412 ,  G11C11/413 ,  G11C15/00

摘要： A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively. The first and second pair of access parameter ports may be adapted to allow access through the first and second pair of access parameter ports if the first access parameter matches a first pre-determined value, and if the second access parameter matches a second pre-determined value.

摘要翻译： 提供了一种方法，装置，计算机芯片，电路板，计算机和系统，其中数据存储在低电压，可屏蔽的存储器中。 还提供了一种用数据编码的计算机可读存储设备，用于使制造设备适配以创建设备。 如果与存储器单元相关联的第一访问参数与第一预定值相匹配，并且如果与存储单元相关联的第二访问参数与第二预定值匹配，则该方法包括将存储单元中的数据值存储在存储设备中 。 如果第一访问参数不同于第一预定值，则该方法还包括在存储设备中的存储单元中维护数据值。 该装置包括分别可操作地耦合在一起并与第一和第二访问参数相关联的第一和第二对访问参数端口。 如果第一访问参数与第一预定值相匹配，则第一和第二对访问参数端口可以被适配为允许通过第一和第二对访问参数端口访问，并且如果第二访问参数与第二预定值 值。

公开(公告)号：US07679402B2

公开(公告)日：2010-03-16

申请号：US12062102

申请日：2008-04-03

申请人： J. Adam Butts ,  Gary S. Ditlow ,  Stephen V. Kosonocky ,  Brian C. Monwai

发明人： J. Adam Butts ,  Gary S. Ditlow ,  Stephen V. Kosonocky ,  Brian C. Monwai

IPC分类号： H03K19/0175

CPC分类号： H03K19/0016

摘要： A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.

摘要翻译： 结合有当前饥饿的环形振荡器的电路被耦合到集成电路中的功率门开关。 结合当前饥饿的环形振荡器的电路放大与电源栅极开关和地之间的虚拟地之间的电压差，并将该差转换成频率。 数字逻辑使用计数器和参考时钟监视环形振荡器的输出。 控制电路根据与功率门开关相关的监控条件控制集成电路的工作。 一种方法监视集成电路中的电源门极开关上的虚拟接地电压; 并且根据所监视的虚拟接地电压来控制集成电路的操作。

公开(公告)号：US20090251171A1

公开(公告)日：2009-10-08

申请号：US12062102

申请日：2008-04-03

申请人： J. Adam Butts ,  Gary S. Ditlow ,  Stephen V. Kosonocky ,  Brian C. Monwai

发明人： J. Adam Butts ,  Gary S. Ditlow ,  Stephen V. Kosonocky ,  Brian C. Monwai

IPC分类号： H03K17/16

CPC分类号： H03K19/0016

摘要： A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.

摘要翻译： 结合有当前饥饿的环形振荡器的电路被耦合到集成电路中的功率门开关。 结合当前饥饿的环形振荡器的电路放大与电源栅极开关和地之间的虚拟地之间的电压差，并将该差转换成频率。 数字逻辑使用计数器和参考时钟监视环形振荡器的输出。 控制电路根据与功率门开关相关的监控条件控制集成电路的工作。 一种方法监视集成电路中的电源门极开关上的虚拟接地电压; 并且根据所监视的虚拟接地电压来控制集成电路的操作。

公开(公告)号：US20080225573A1

公开(公告)日：2008-09-18

申请号：US12130257

申请日：2008-05-30

申请人： Azeez Bhavnagarwala ,  Stephen V. Kosonocky ,  Sampath Purushothaman ,  Kenneth P. Rodbell

发明人： Azeez Bhavnagarwala ,  Stephen V. Kosonocky ,  Sampath Purushothaman ,  Kenneth P. Rodbell

IPC分类号： G11C11/00

CPC分类号： G11C11/4125 ,  Y10S257/903

摘要： A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.

摘要翻译： 存储单元包括字线，具有第一输入和第一输出的第一数字逆变器以及具有第二输入和第二输出的第二数字反相器。 此外，存储单元还包括将第一输出连接到第二输入的第一反馈连接和将第二输出连接到第一输入的第二反馈连接。 第一反馈连接包括第一电阻元件，第二反馈连接包括第二电阻元件。 更重要的是，每个数字逆变器都有相关的电容。 存储单元被配置为使得读取存储器单元包括将读取电压脉冲施加到字线。 此外，第一和第二电阻元件被配置为使得第一和第二反馈连接具有比施加的读取电压脉冲更长的电阻 - 电容感应延迟。

公开(公告)号：US20080023731A1

公开(公告)日：2008-01-31

申请号：US11496120

申请日：2006-07-31

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip George Emma ,  Allan Mark Hartstein ,  Stephen V. Kosonocky ,  Ruchir Puri ,  Mark B. Ritter

IPC分类号： H01L29/80

CPC分类号： G11C5/063 ,  G11C5/14 ,  H01L21/8221 ,  H01L27/0688 ,  H03H1/0007

摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

摘要翻译： 具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

公开(公告)号：US07127560B2

公开(公告)日：2006-10-24

申请号：US10605616

申请日：2003-10-14

申请人： Erwin B. Cohen ,  Thomas E. Cook ,  Ian R. Govett ,  Paul D. Kartschoke ,  Stephen V. Kosonocky ,  Peter A. Sandon ,  Keith R. Williams

发明人： Erwin B. Cohen ,  Thomas E. Cook ,  Ian R. Govett ,  Paul D. Kartschoke ,  Stephen V. Kosonocky ,  Peter A. Sandon ,  Keith R. Williams

IPC分类号： G06F12/00

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G06F12/0804 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20 ,  Y10S707/99952

摘要： A power saving cache and a method of operating a power saving cache. The power saving cache includes circuitry to dynamically reduce the logical size of the cache in order to save power. Preferably, a method is used to determine optimal cache size for balancing power and performance, using a variety of combinable hardware and software techniques. Also, in a preferred embodiment, steps are used for maintaining coherency during cache resizing, including the handling of modified (“dirty”) data in the cache, and steps are provided for partitioning a cache in one of several way to provide an appropriate configuration and granularity when resizing.

摘要翻译： 省电缓存和操作省电高速缓存的方法。 省电高速缓存包括用于动态地减小高速缓存的逻辑大小以节省功率的电路。 优选地，使用各种可组合的硬件和软件技术来使用一种方法来确定用于平衡功率和性能的最佳高速缓存大小。 此外，在优选实施例中，步骤用于在高速缓存调整大小期间维持一致性，包括对高速缓存中的修改（“脏”）数据的处理，并且提供了用于以多种方式之一对高速缓存进行分区以提供适当配置的步骤 调整大小时的粒度。

公开(公告)号：US06999370B2

公开(公告)日：2006-02-14

申请号：US10635331

申请日：2003-08-06

申请人： Wing K. Luk ,  Robert H. Dennard ,  Stephen V. Kosonocky

发明人： Wing K. Luk ,  Robert H. Dennard ,  Stephen V. Kosonocky

IPC分类号： G11C7/00

CPC分类号： G11C5/063 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/104

摘要： An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.

摘要翻译： 诸如存储器宏的集成电路包括支持第一和第二电压差的多个电源轨，第二电压差小于第一电压差。 集成电路中的信号线由小的摆动电路产生的小电压摆动驱动。 集成电路还包括正在接收小电压摆幅输入并且正在输出第一或全电压摆幅的再生电路。 将小电压摆幅应用于信号线节省了集成电路中的功率。 宽带宽全字I / O存储器集成电路在连接到同一字线和对应的I / O端子的基本上所有的存储器单元之间具有同时可操作的连接路径，并且具有单端数据线结构 。

公开(公告)号：US06977519B2

公开(公告)日：2005-12-20

申请号：US10437764

申请日：2003-05-14

申请人： Azeez J. Bhavnagarwala ,  Suhwan Kim ,  Daniel R. Knebel ,  Stephen V. Kosonocky

发明人： Azeez J. Bhavnagarwala ,  Suhwan Kim ,  Daniel R. Knebel ,  Stephen V. Kosonocky

IPC分类号： H03K19/00 ,  H03K17/16

CPC分类号： H03K19/0016

摘要： A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source to source and drain to drain, respectively, a ground node in signal communication with the drains of the transistors, and a ground rail in signal communication with the sources of the transistors; and the corresponding method includes decoupling the logic circuit from the ground connection in a first or active mode, holding the logic circuit at about a threshold voltage above the ground connection in a second or state retention mode, and cutting off the current flow between the logic circuit and the ground connection in a third or non-state retentive mode.

摘要翻译： 提供了功率门结构和相应的方法，用于控制用于多个模式的逻辑电路的接地连接，其中功率栅极结构包括NFET晶体管，与NFET晶体管信号通信的PFET晶体管，源极和漏极 分别与晶体管的漏极信号通信的接地节点和与晶体管的源极信号通信的接地轨道; 并且相应的方法包括在第一或活动模式下将逻辑电路与接地连接解耦，在第二或状态保持模式下将逻辑电路保持在接地连接以上的阈值电压处，并且切断逻辑电流之间的电流 电路和接地连接处于第三或非状态保持模式。