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    Memory device and method for fabricating the same
    21.
    发明授权
    Memory device and method for fabricating the same 有权
    存储器件及其制造方法

    公开(公告)号：US09466792B2

    公开(公告)日：2016-10-11

    申请号：US14623654

    申请日：2015-02-17

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee

    IPC: H01L45/00

    CPC classification number: H01L45/124 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1633

    Abstract: A memory device comprises a substrate, a first electrode layer, a spacer, a memory layer and a second electrode layer. The substrate has a recess. The first electrode layer is formed in the recess and has a top surface exposed from an opening of the recess. The spacer covers on a portion of the top surface, so as to define a contact area on the top surface. The memory layer is formed on the contact area. The second electrode layer is formed on the memory layer and electrically connected to the memory layer.

    Abstract translation: 存储器件包括衬底，第一电极层，间隔物，存储层和第二电极层。 衬底具有凹部。 第一电极层形成在凹部中并且具有从凹部的开口露出的顶表面。 间隔件覆盖在顶表面的一部分上，以便限定顶表面上的接触区域。 存储层形成在接触区域上。 第二电极层形成在存储层上并与存储层电连接。

    Memory device for in-memory computing
    24.
    发明授权
    Memory device for in-memory computing 有权

    公开(公告)号：US12142316B2

    公开(公告)日：2024-11-12

    申请号：US17812783

    申请日：2022-07-15

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Ming-Hsiu Lee

    IPC: G11C13/00 ,  G06F7/544

    Abstract: A memory device includes a plurality of computing memory cells, each of which stores a weight value, receives an input value and generates an output value. Each of the computing memory cells includes a transistor connected to a bit line and a word line, receiving a sensing current through the bit line and receiving an input voltage through the word line. When the sensing current flows through the transistor, the computing memory cell generates a first voltage difference corresponding to the output value. The output value is equal to a product of the input value and the weight value.

    NEUROMORPHIC COMPUTING DEVICE
    25.
    发明申请
    NEUROMORPHIC COMPUTING DEVICE 审中-公开

    公开(公告)号：US20190156883A1

    公开(公告)日：2019-05-23

    申请号：US15817437

    申请日：2017-11-20

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee

    IPC: G11C11/54 ,  G11C13/00 ,  G06N3/063 ,  G06F7/544

    Abstract: A neuromorphic computing device includes a plurality of row lines, a plurality of column lines and a plurality of synapses. The synapses are positioned at intersections of the row lines and column lines, respectively. The synapses include a first synapse and a second synapse. The first synapse includes a first resistance-adjustable element and a first transistor connected to the first resistance-adjustable element in series. The first transistor has a first aspect ratio and is configured to receive a first turn-on voltage. The second synapse includes a second resistance-adjustable element and a second transistor connected to the second resistance-adjustable element in series. The second transistor has a second aspect ratio and is configured to receive a second turn-on voltage. The first aspect ratio differs from the second aspect ratio, and/or the first turn-on voltage differs from the second turn-on voltage.

    Device structure for neuromorphic computing system
    27.
    发明授权
    Device structure for neuromorphic computing system 有权

    公开(公告)号：US10242737B1

    公开(公告)日：2019-03-26

    申请号：US15895369

    申请日：2018-02-13

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee

    IPC: G11C13/00 ,  H01L27/24 ,  G06N3/063 ,  H01L45/00

    Abstract: An array of resistance cells has a number M of rows and a number N of columns of resistance cells. Each cell comprises a transistor having a threshold, representing a weight factor Wnm of the cell, and a resistive element in series with the transistor. Each cell has a cell resistance having a first value when the transistor is on and a second value when the transistor is off. A set of source lines is coupled to the resistance cells in respective columns. A set of bit lines is coupled to the resistance cells in respective rows, signals on the bit lines representing inputs x(m) to the respective rows. A set of word lines is coupled to gates of the transistors in the resistance cells in respective columns. Current sensed at a particular source line represents a sum of products of the inputs x(m) by respective weight factors Wnm.

    Resistive random access memory device and method for manufacturing the same
    28.
    发明授权
    Resistive random access memory device and method for manufacturing the same 有权

    公开(公告)号：US10115769B1

    公开(公告)日：2018-10-30

    申请号：US15620880

    申请日：2017-06-13

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Po-Hao Tseng ,  Feng-Min Lee ,  Yu-Yu Lin ,  Kai-Chieh Hsu

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A ReRAM device is provided. The ReRAM device comprises a first dielectric layer disposed on a substrate and covering a gate oxide structure on the substrate, a first conductive connecting structure disposed on the substrate and penetrating the first dielectric layer, and a ReRAM unit disposed on the first conductive connecting structure. The first dielectric layer comprises a first insulating layer disposed on the substrate, and a stop layer disposed on the first insulating layer and contacting a top surface of the gate oxide structure, wherein the stop layer is a hydrogen controlled layer.

    Method for operating non-volatile memory device and applications thereof
    29.
    发明授权
    Method for operating non-volatile memory device and applications thereof 有权

    公开(公告)号：US09947403B1

    公开(公告)日：2018-04-17

    申请号：US15469672

    申请日：2017-03-27

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Kai-Chieh Hsu

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0073 ,  G11C2013/0092

    Abstract: A method for operating a resistance switching memory device is provided, wherein the method includes a first program process, and the first program process includes steps as follows: A programming pulse having a first polarity is firstly applied to at least one resistance switching memory cell of the NVM device. A first verifying pulse with a verifying voltage is then applied to the resistance switching memory cell. A first settling pulse is applied to the resistance switching memory cell prior to or after the verifying pulse is applied, wherein the first settling pulse includes a settling voltage having a second polarity opposite to the first polarity and an absolute value substantially less than that of the verifying voltage.

    Semiconductor memory device and operation method thereof
    30.
    发明授权
    Semiconductor memory device and operation method thereof 有权

    公开(公告)号：US09947398B1

    公开(公告)日：2018-04-17

    申请号：US15482978

    申请日：2017-04-10

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Hsuan Lin ,  Kai-Chieh Hsu ,  Yu-Yu Lin ,  Feng-Min Lee

    IPC: G11C11/00 ,  G11C13/00 ,  G06F1/32

    CPC classification number: G11C13/0038 ,  G11C13/004 ,  G11C2013/0054

    Abstract: A semiconductor memory device includes: a memory array including a plurality of memory cells, the memory cells being in any of a high resistance state (HRS) and a low resistance state (LRS); a reference array including a plurality of reference cells, the memory cells and the reference cells having the same impedance-temperature relationship, the reference cells being in a middle resistance state between HRS and LRS; an average circuit configured for averaging respective reference currents from the reference cells of the reference array into an average reference current; and a comparator configured for comparing a plurality of respective memory currents from the memory cells of the memory array with the average reference current to obtain a plurality of output data of the memory cells of the memory array and to determine respective impedance states of the memory cells of the memory array.

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