公开(公告)号：US11494095B1

公开(公告)日：2022-11-08

申请号：US17368579

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Deping He

IPC: G06F12/00 ,  G06F3/06

Abstract: A method includes receiving, by a processing device, signaling indicative of a power cycle (PC) to a memory device (MD) having a first signal indicative of a Power On Operation and a second signal indicative of a Power Off Operation, and determining an Average Power On Time (APOT) of the MD based, at least in part, on a quantity of power cycles (n) to the MD over a predetermined time interval (PTI), and for each PC over the PTI, an amount of time between receipt of the first signal and the second signal. A sum of each of the amount of time between receipt of the first signal and the second signal in the PTI provides a total power on time (T) to the MD, and the APOT is equal to T/n. When the APOT is less than (

公开(公告)号：US11321176B2

公开(公告)日：2022-05-03

申请号：US17004136

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/408 ,  G06F11/30 ,  G06F11/07

Abstract: A method includes receiving, by a memory sub-system, host data to be written to a plurality of blocks of a memory device associated with a memory sub-system, where each of the plurality of blocks are coupled to one of a plurality of word lines of the memory device. The method can further include generating parity data for each word line of the block; dividing the parity data into one of either a first word line parity set or a second word line parity set; generating a reduced parity data set with exclusive or parity values for the first word line parity set and for the second word line parity set; and writing the reduced parity data set in the memory sub-system.

公开(公告)号：US20210233594A1

公开(公告)日：2021-07-29

申请号：US17301743

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Devin M. Batutis ,  Avinash Rajagiri ,  Sheng-Huang Lee ,  Chun Sum Yeung ,  Harish R. Singidi

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10

Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

公开(公告)号：US20210191807A1

公开(公告)日：2021-06-24

申请号：US16723836

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

IPC: G06F11/10 ,  G06F11/07 ,  G06F12/02 ,  G06F12/0882

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20250130894A1

公开(公告)日：2025-04-24

申请号：US18776314

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Lei Lin ,  Guang Hu ,  Chun Sum Yeung ,  Dongxiang Liao ,  Xiangang Luo

IPC: G06F11/10

Abstract: Various embodiments provide for dynamically enabling and disabling foreground scans of blocks of a memory device, which can be part of a memory sub-system. For instance, some embodiments provide an improved methodology for triggering foreground media scans of blocks of a memory device without disturbing a maximum idea time of background media scans of blocks of the memory device.

公开(公告)号：US20240411475A1

公开(公告)日：2024-12-12

申请号：US18812356

申请日：2024-08-22

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Chun Sum Yeung ,  Kulachet Tanpairoj

IPC: G06F3/06

Abstract: An apparatus can include a block program erase count (PEC) component. The block PEC component can monitor a quantity of program erase counts (PECs) for each particular type of block of a non-volatile memory array. The block PEC component can further determine which block of the superblock to write host data to next based on the quantity of PECs. The block PEC component can further write host data to the determined block.

公开(公告)号：US20240385751A1

公开(公告)日：2024-11-21

申请号：US18787528

申请日：2024-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chun Sum Yeung ,  Deping He ,  Ting Luo ,  Guang Hu ,  Jonathan S. Parry

IPC: G06F3/06

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a program-erase cycle count associated with at least a portion of the plurality of memory cells. The processing device is further to erase, based on the value of the PEC count, less than a predetermined portion of free sets of memory cells to form an erased set of memory cells. The processing device is further to receive a programming command directed to at least a portion of the erased set of memory cells. The processing device is further to perform a programming operation with respect to the at least a portion of the erased set of memory cells.

公开(公告)号：US20240363185A1

公开(公告)日：2024-10-31

申请号：US18656177

申请日：2024-05-06

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry ,  Chun Sum Yeung

IPC: G11C29/42 ,  G06F11/07 ,  G11C29/12 ,  G11C29/20 ,  G11C29/44

CPC classification number: G11C29/42 ,  G06F11/076 ,  G11C29/1201 ,  G11C29/20 ,  G11C29/4401

Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

公开(公告)号：US20240339172A1

公开(公告)日：2024-10-10

申请号：US18624720

申请日：2024-04-02

Applicant: Micron Technology, Inc.

Inventor： Yugang Yu ,  Chun Sum Yeung ,  Pitamber Shukla

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/022 ,  G11C29/028

Abstract: Aspects of the present disclosure are directed to a memory sub-system using a block family error avoidance (BFEA) scan to adjust read voltages. Three-level cell (TLC) memory stores three bits per cell. Due to variances in manufacturing and degradation over time, the actual voltages stored in the memory cells deviate from the target voltages. As a result, the comparisons between the read voltages and the stored voltages may generate erroneous results. A BFEA scan may be based on a single wordline and single page type. However, determining a single threshold voltage shift to apply to all read voltages may not compensate for all causes of voltage shifting. Accordingly, a BFEA scan may use multiple wordlines (e.g., one for each page) and determine different voltage offset values for each page. As a result, the accuracy of the read voltage applied is increased and the bit error rate (BER) is reduced.

公开(公告)号：US20240069776A1

公开(公告)日：2024-02-29

申请号：US18237737

申请日：2023-08-24

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Hong Lu ,  Kulachet Tanpairoj ,  Chun Sum Yeung ,  Jameer Mulani ,  Nitul Gohain ,  Uday Bhasker V. Vudugandla

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0673

Abstract: A system can include a memory device with multiple management units, each management unit made up of multiple blocks, and a processing device, operatively coupled with the memory device, to perform various operations including identifying, among the management units, some complete management units and some incomplete management units, as well as performing one type of operation using one or more complete management units. The operations can also include performing another type of operation using one or more incomplete management units where this other type of operation include writing, to one or more incomplete management units, metadata associated with the data stored in complete management units.