公开(公告)号：US20200090732A1

公开(公告)日：2020-03-19

申请号：US16690598

申请日：2019-11-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  David R. Brown ,  Gary L. Howe

IPC: G11C11/4093 ,  G11C7/10

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

公开(公告)号：US20190164593A1

公开(公告)日：2019-05-30

申请号：US15826236

申请日：2017-11-29

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  David R. Brown ,  Gary L. Howe

IPC: G11C11/4093 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C7/1093 ,  G11C7/1096 ,  G11C11/4076 ,  G11C2207/2254

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

公开(公告)号：US10013197B1

公开(公告)日：2018-07-03

申请号：US15611369

申请日：2017-06-01

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe ,  Harish N. Venkata

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/08 ,  G11C7/10

CPC classification number: G06F3/0635 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0683 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1012 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16

Abstract: The present disclosure includes apparatuses and methods related to a shift skip. An example apparatus comprises a plurality of sensing circuitries, comprising respective sense amplifiers and respective compute components. A controller is configured to, responsive to a mask data unit associated with a first sensing circuitry having a particular value, cause a data value to be shifted from a second sensing circuitry to a third sensing circuitry without shifting the data value to the first sensing circuitry, wherein the first sensing circuitry is physically located between the second sensing circuitry and the third sensing circuitry.

公开(公告)号：US12197264B2

公开(公告)日：2025-01-14

申请号：US17094579

申请日：2020-11-10

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Gary L. Howe ,  Miles S. Wiscombe ,  Eric J. Stave

IPC: G06F1/32 ,  G06F1/3203 ,  G11C11/40 ,  G11C11/4074

Abstract: Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.

公开(公告)号：US11908509B2

公开(公告)日：2024-02-20

申请号：US17701950

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： John E. Riley ,  Scott E. Smith ,  Jennifer E. Taylor ,  Gary L. Howe

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096

Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.

公开(公告)号：US11755206B2

公开(公告)日：2023-09-12

申请号：US17178889

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G06F3/06 ,  G11C8/00 ,  G06F13/16

CPC classification number: G06F3/061 ,  G06F3/0625 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/161 ,  G11C8/00 ,  Y02D10/00

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US20230021201A1

公开(公告)日：2023-01-19

申请号：US17939908

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Miles S. Wiscombe ,  James S. Rehmeyer ,  Eric J. Stave

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074 ,  G11C5/14

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

公开(公告)号：US11417374B1

公开(公告)日：2022-08-16

申请号：US17178475

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： William Chad Waldrop ,  Gary L. Howe

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4076

Abstract: Systems and methods described herein provide decision feedback equalizer (DFE) circuitry that includes one or more phases. The one or more phases receive bit feedback at respective inputs of the phases. The DFE circuitry also may include variable reset circuitry. The variable reset circuitry may reset voltages of the bit feedback at inputs of each of the phases. The variable reset circuitry is configured to change its reset frequency between resets.

公开(公告)号：US20220107905A1

公开(公告)日：2022-04-07

申请号：US17062484

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Vaughn N. Johnson ,  Kyle Alexander ,  Gary L. Howe ,  Brian T. Pecha ,  Miles S. Wiscombe

IPC: G06F13/16 ,  G11C11/4096 ,  G11C11/406

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

公开(公告)号：US10733089B2

公开(公告)日：2020-08-04

申请号：US15215296

申请日：2016-07-20

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Timothy P. Finkbeiner

IPC: G06F12/02

Abstract: Apparatuses and methods are provided for write address tracking. An example apparatus can include an array of memory cells and a cache coupled to the array. The example apparatus can include tracking circuitry coupled to the cache. The tracking circuitry can be configured to track write addresses of data written to the cache.