公开(公告)号：US20150134898A1

公开(公告)日：2015-05-14

申请号：US14599892

申请日：2015-01-19

Applicant: Micron Technology, Inc.

Inventor： Harold B. Noyes ,  Mark Jurenka ,  Gavin Huggins

IPC: G11C7/10 ,  G06F12/06

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34 ,  G06F12/0615 ,  G06F2212/656

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

Abstract translation: 提供了系统和方法来管理对寄存器的访问。 在一个实施例中，系统可以包括处理器和多个寄存器。 处理器和多个寄存器可以集成到单个设备中，或者可以在单独的设备中。 多个寄存器可以包括可由处理器直接访问的第一组寄存器和不能由处理器直接访问的第二组寄存器。 然而，第二组寄存器可以由处理器经由第一组寄存器间接访问。 在一个实施例中，第一组寄存器可以包括用于从第二组寄存器中选择寄存器组的寄存器和用于选择寄存器组中的特定地址的寄存器，以允许处理器间接访问寄存器组的寄存器 第二集

公开(公告)号：US20140204956A1

公开(公告)日：2014-07-24

申请号：US14223507

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B. Noyes ,  Irene Junjuan Xu ,  Paul Glendenning

IPC: G06K9/00 ,  H04L12/883

CPC classification number: G06F13/1673 ,  G06F9/4498 ,  G06F13/124 ,  G06F13/4022 ,  G06F13/4282 ,  G06F17/30516 ,  G06K9/00496 ,  G06K9/00973 ,  G06K9/00979 ,  H04L49/9021

Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.

Abstract translation: 设备包括路由缓冲区。 路由缓冲器包括被配置为接收与数据流的至少一部分的分析有关的信号的第一端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第一路由线的第二端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第二路由选择线的第三端口。

公开(公告)号：US20130290235A1

公开(公告)日：2013-10-31

申请号：US13928171

申请日：2013-06-26

Applicant: Micron Technology, Inc.

Inventor： Paul D. Dlugosch ,  Harold B. Noyes

IPC: G06N5/02

CPC classification number: G06N5/022 ,  H04L63/0245

Abstract: Methods and apparatus are provided involving adaptive content inspection. In one embodiment, a content inspection processor may identify information with respect to input data and provide the information to a host controller. The host controller may adapt search criteria or other parameters and provide the adapted parameter to the content inspection processor. Other embodiments may include a content inspection processor having integrated feedback, such that results data is fed back to the content inspection processor. The results data may be processed before being provided to the content inspection processor.

Abstract translation: 提供了涉及自适应内容检查的方法和装置。 在一个实施例中，内容检查处理器可以识别关于输入数据的信息，并将信息提供给主机控制器。 主机控制器可以调整搜索标准或其他参数，并将适配参数提供给内容检查处理器。 其他实施例可以包括具有集成反馈的内容检查处理器，使得结果数据被反馈到内容检查处理器。 可以在提供给内容检查处理器之前处理结果数据。

公开(公告)号：US20230176999A1

公开(公告)日：2023-06-08

申请号：US18103957

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Harold B. Noyes ,  David R. Brown ,  Paul Glendenning ,  Paul D. Dlugosch

IPC: G06F15/78 ,  G06N20/00 ,  G06F9/448 ,  G06F1/3225 ,  G06F13/42

CPC classification number: G06F15/7867 ,  G06N20/00 ,  G06F9/4498 ,  G06F1/3225 ,  G06F13/423 ,  G06F15/7857 ,  G05B19/045

Abstract: A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.

公开(公告)号：US20210149810A1

公开(公告)日：2021-05-20

申请号：US17155433

申请日：2021-01-22

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B. Noyes ,  Inderjit Singh Bains

IPC: G06F12/0875 ,  G06F3/06 ,  G06F9/448 ,  G06N3/02

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

公开(公告)号：US20170351631A1

公开(公告)日：2017-12-07

申请号：US15683649

申请日：2017-08-22

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B. Noyes ,  Inderjit S. Bains

IPC: G06F13/40 ,  G06F9/44 ,  G06F15/78 ,  G06N3/08

CPC classification number: G06F13/4027 ,  G06F9/4498 ,  G06F15/7867 ,  G06N3/08

Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

公开(公告)号：US20170345467A1

公开(公告)日：2017-11-30

申请号：US15676796

申请日：2017-08-14

Applicant: Micron Technology, Inc.

Inventor： Harold B. Noyes ,  Mark Jurenka ,  Gavin Huggins

IPC: G11C7/10 ,  G06F12/06 ,  G06F9/30 ,  G06F9/34

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34 ,  G06F12/0615 ,  G06F2212/656

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

公开(公告)号：US20160124860A1

公开(公告)日：2016-05-05

申请号：US14992616

申请日：2016-01-11

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B. Noyes ,  Inderjit Singh Bains

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0875 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0683 ,  G06F9/4498 ,  G06F2212/60 ,  G06N3/02

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

Abstract translation: 数据分析系统分析数据。 数据分析系统包括被配置为接收待分析数据的数据缓冲器。 数据分析系统还包括状态机格。 状态机格子包括多个数据分析元素，并且每个数据分析元件包括配置成分析数据的至少一部分并输出分析结果的多个存储器单元。 数据分析系统包括配置成从数据缓冲器接收数据并将数据提供给状态机格的缓冲接口。

公开(公告)号：US20150253755A1

公开(公告)日：2015-09-10

申请号：US14722941

申请日：2015-05-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Harold B. Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G05B19/045 ,  H03K19/177

CPC classification number: G05B19/045 ,  G06F9/4498 ,  G06F15/82 ,  G06F21/567 ,  G06F2207/025 ,  G06N5/047 ,  H03K19/17724 ,  H03K19/17748

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 格子可以包括适合于对格子中的可编程元件检测到条件的次数进行计数的计数器。 计数器可以配置为响应于计数而输出，条件被检测到一定次数。 例如，计数器可以被配置为响应于确定至少（或不多于）一定次数检测到的条件而输出，确定条件被精确地检测到一定次数，或者确定检测到条件 在一定的时间范围内。 计数器可以耦合到设备中的其他计数器，用于确定高计数操作和/或某些量化器。