公开(公告)号：US20190043884A1

公开(公告)日：2019-02-07

申请号：US16106693

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Charles H. Dennison ,  Gordon A. Haller ,  Merri L Carlson ,  John D. Hopkins ,  Jia Hui Ng ,  Jie Sun

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/788 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/792

Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method.

公开(公告)号：US10038002B2

公开(公告)日：2018-07-31

申请号：US15296858

申请日：2016-10-18

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L21/311 ,  H01L21/28 ,  H01L21/285 ,  H01L27/1157

CPC classification number: H01L27/11556 ,  H01L21/31111 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/513 ,  H01L29/66825

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US20180040626A1

公开(公告)日：2018-02-08

申请号：US15229490

申请日：2016-08-05

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Charles H. Dennison ,  Gordon A. Haller ,  Merri L. Carlson ,  John D. Hopkins ,  Jia Hui Ng ,  Jie Sun

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/02282 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11556 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method.

公开(公告)号：US20160336341A1

公开(公告)日：2016-11-17

申请号：US15221131

申请日：2016-07-27

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L27/115 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/7889

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

公开(公告)号：US20150064871A1

公开(公告)日：2015-03-05

申请号：US14534454

申请日：2014-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John Hopkins ,  James Matthew ,  Jie Sun ,  Gordon Haller

IPC: H01L21/762 ,  H01L27/115

CPC classification number: H01L21/76224 ,  H01L27/11524 ,  H01L27/1157

Abstract: An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

Abstract translation: 一个实施例包括在半导体中在第一和第二有源区之间形成隔离区，通过去除隔离区的一部分形成第一和第二有源区之间的开口，以及在该开口内形成电介质塞， 在第一和第二有源区之间并且使得电介质塞的一部分延伸到第一和第二有源区的上表面之下。 电介质插塞可以由对于特定的各向同性的去除化学物质具有比隔离区域的电介质材料更低的去除速率的电介质材料形成。

公开(公告)号：US20210366931A1

公开(公告)日：2021-11-25

申请号：US17397338

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US20200227427A1

公开(公告)日：2020-07-16

申请号：US16834291

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/66

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US10388668B2

公开(公告)日：2019-08-20

申请号：US16184907

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

公开(公告)号：US20190131315A1

公开(公告)日：2019-05-02

申请号：US16132984

申请日：2018-09-17

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatam Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11556 ,  H01L29/66 ,  H01L27/11524 ,  H01L29/788

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

公开(公告)号：US20170012053A1

公开(公告)日：2017-01-12

申请号：US15248968

申请日：2016-08-26

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

Abstract translation: 一些实施例包括具有交替介电水平和导电水平的叠层，导电水平内的垂直堆叠的存储单元，堆叠上的绝缘材料和绝缘材料上的选择栅极材料的集成结构。 开口延伸穿过选择栅材料，穿过绝缘材料，并通过交替的电介质层和导电层叠。 绝缘材料内的开口的第一区域沿着选择栅极材料内的开口的第二区域的横截面较宽，并且沿着横截面比在交替堆叠内的开口的第三区域更宽 介电水平和导电水平。 通道材料在开口内并且与绝缘材料，选择栅极材料和存储单元相邻。 一些实施例包括形成垂直堆叠的存储器单元的方法。