公开(公告)号：US20210408039A1

公开(公告)日：2021-12-30

申请号：US17468170

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Cole Smith ,  Ramey M. Abdelrahaman ,  Silvia Borsari ,  Chris M. Carlson ,  David Daycock ,  Matthew J. King ,  Jin Lu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

公开(公告)号：US11011420B2

公开(公告)日：2021-05-18

申请号：US16773716

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Jin Lu ,  Shyam Ramalingam

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/288 ,  H01L21/48

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

公开(公告)号：US20210111184A1

公开(公告)日：2021-04-15

申请号：US16653062

申请日：2019-10-15

Applicant: Micron Technology, Inc.

Inventor： Cole Smith ,  Ramey M. Abdelrahaman ,  Silvia Borsari ,  Chris M. Carlson ,  David Daycock ,  Matthew J. King ,  Jin Lu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

公开(公告)号：US20180204803A1

公开(公告)日：2018-07-19

申请号：US15405711

申请日：2017-01-13

Applicant: Micron Technology, Inc.

Inventor： Gregory C. Herdt ,  Mikhail A. Treger ,  Jin Lu

IPC: H01L23/532 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76856 ,  H01L21/76898 ,  H01L23/481

Abstract: Semiconductor device interconnect structures comprising nitrided barriers are disclosed herein. In one embodiment, an interconnect structure includes a conductive material at least partially filling an opening in a semiconductor substrate, and a nitrided barrier between the conductive material and a sidewall in the opening. The nitrided barrier comprises a nitride material and a barrier material, such as tantalum, between the nitride material and the sidewall of the substrate.

公开(公告)号：US20180174902A1

公开(公告)日：2018-06-21

申请号：US15889120

申请日：2018-02-05

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Jin Lu ,  Shyam Ramalingam

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/288

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

公开(公告)号：US20150340282A1

公开(公告)日：2015-11-26

申请号：US14815560

申请日：2015-07-31

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Jin Lu ,  Shyam Ramalingam

IPC: H01L21/768 ,  H01L21/288

CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract translation: 本文公开了具有并入负扩张（NTE）材料的互连的半导体器件。 在一个实施例中，半导体器件包括具有至少部分延伸穿过衬底的开口的衬底。 具有正的热膨胀系数（CTE）的导电材料部分地填充开口。 具有负CTE的负热膨胀（NTE）也部分填充开口。 在一个实施例中，导电材料包括铜，NTE材料包括钨酸锆。

公开(公告)号：US09153451B2

公开(公告)日：2015-10-06

申请号：US13712635

申请日：2012-12-12

Applicant: Micron Technology, Inc.

Inventor： Andrew Dennis Watson Carswell ,  Wayne Hai-Wei Huang ,  Siddartha Kondoju ,  Jin Lu ,  Suresh Ramakrishnan ,  Kozaburo Sakai ,  Sony Varghese ,  Andrey V. Zagrebelny

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L21/30625 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/32125

Abstract: A method of forming a planar surface for a semiconductor device structure. The method comprises forming a particle film comprising a plurality of discrete particles on a non-planar surface of a semiconductor device structure. The semiconductor device structure is subjected to at least one chemical-mechanical polishing process after forming the particle film on the non-planar surface of the semiconductor device structure. Methods of forming a semiconductor device structure are also described.

Abstract translation: 一种形成半导体器件结构的平面的方法。 该方法包括在半导体器件结构的非平面表面上形成包含多个离散粒子的粒子膜。 半导体器件结构在半导体器件结构的非平面表面上形成颗粒膜之后经历至少一个化学机械抛光工艺。 还描述了形成半导体器件结构的方法。

公开(公告)号：US20150035150A1

公开(公告)日：2015-02-05

申请号：US13959429

申请日：2013-08-05

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Jin Lu ,  Shyam Ramalingam

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract translation: 本文公开了具有并入负扩张（NTE）材料的互连的半导体器件。 在一个实施例中，半导体器件包括具有至少部分延伸穿过衬底的开口的衬底。 具有正的热膨胀系数（CTE）的导电材料部分地填充开口。 具有负CTE的负热膨胀（NTE）也部分填充开口。 在一个实施例中，导电材料包括铜，NTE材料包括钨酸锆。